Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. - Jiaping Tang; Zizhen Liu; Jianan Mu; Feng Gu; Mingjun Wang; Wenxing Li; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (ATS, 2024)

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. - Feng Gu; Mingjun Wang; Jianan Mu; Zizhen Liu; Jiaping Tang; Hui Wang 152; Yonghao Wang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. - Mingjun Wang; Hui Wang 152; Zizhen Liu; Feng Gu; Jianan Mu; Jiaping Tang; Jun Gao; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ASP-DAC, 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shenwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2025)

Extend IVerilog to Support Batch RTL Fault Simulation. - Jiaping Tang; Jianan Mu; Zizhen Liu; Zhiteng Chao; Jing Ye 001; Huawei Li 001 (CoRR, 2025)