A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs. - Haoxiang Zhou; Zikun Wei; Dingbang Liu; Liuyang Zhang; Chenchen Ding; Jiaqi Yang 009; Wei Mao 002; Hao Yu 001 (ASP-DAC, 2025)

A 20.98TOPS/W Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator. - Dingbang Liu; Ziyi Guan; Qilong Chen; Jingyun Gu; Jiaqi Yang 009; Kai Li 024; Wei Mao 002; Ngai Wong 001; Changwen Chen; Hao Yu 001 (ISLPED, 2025)

A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity. - Wei Mao 002; Dingbang Liu; Haoxiang Zhou; Fuyi Li; Kai Li 024; Qiuping Wu; Jiaqi Yang 009; Quan Cheng; Liuyang Zhang; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

M3DKV: Monolithic 3D Gain Cell Memory Enabled Efficient KV Cache & Processing. - Jiaqi Yang 009; Yanbo Su; Yihan Fu; Jianshi Tang; Bonan Yan (ASP-DAC, 2026)

ESTroM: Element-Flow Architecture for Processing Sparse Tractable Probabilistic Models. - Anjunyi Fan; Xuejie Liu; Anji Liu; Qiuping Wu; Jiaqi Yang 009; Yuchao Qin; Guy Van den Broeck; Yitao Liang; Bonan Yan (HPCA, 2026)