An Approximate Flow Betweenness Centrality Measure for Complex Network. - Jia-Rui Liu 001; Shize Guo; Zhe-Ming Lu 001; Fa-Xin Yu; Hui Li (IEICE Trans. Inf. Syst., 2013)

A New Digital to Analog Converter Based on Low-Offset Bandgap Reference. - Jinpeng Qiu; Tong Liu; Xubin Chen; Yong-Heng Shang; Jiongjiong Mo; Zhiyu Wang 001; Hua Chen 003; Jiarui Liu 001; Jingjing Lv; Fa-Xin Yu (J. Electr. Comput. Eng., 2017)

Design of a broadband Ka-band MMIC LNA using deep negative feedback loop. - Gang Wang; Wei Chen; Jiarui Liu 001; Jiongjiong Mo; Hua Chen 003; Zhiyu Wang 001; Fa-Xin Yu (IEICE Electron. Express, 2018)

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS. - Xubin Chen; Xuan Li; Yupeng Shen; Jiarui Liu 001; Hua Chen 003 (IEICE Electron. Express, 2019)

A 0.07-3 GHz wideband front-end for SDR receiver with 2.3 dB NF and 12 dBm IIP3 in 65 nm CMOS. - Yupeng Shen; Haoming Li 004; Xubin Chen; Jiarui Liu 001; Hua Chen 003 (IEICE Electron. Express, 2019)

An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers. - Fengjie Wang; Liyi Fan; Yupeng Shen; Hua Chen 003; Jiarui Liu 001; Zhiyu Wang 001; Fa-Xin Yu (IEICE Electron. Express, 2019)

A 210fs RMS jitter 187.5 MHz-3GHz fractional-N frequency synthesizer with quantization noise suppression techniques and chopping differential charge pump for SDR applications. - Haoming Li 004; Yupeng Shen; Tengjia Wang; Jiarui Liu 001 (Microelectron. J., 2019)

A highly linear 10 Gb/s MOS current mode logic driver with large output voltage swing based on an active inductor. - Tengjia Wang; Min Zhou; Jiarui Liu 001; Zhiyu Wang 001; Jiongjiong Mo; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2020)

A 92 fsrms jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control. - Jiahao Chen; Haoming Li 004; Tengjia Wang; Zhiyu Wang 001; Hua Chen 003; Jiarui Liu 001; Faxin Yu (IEICE Electron. Express, 2021)

A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS. - Mingliang Chen; Keke Wu; Yupeng Shen; Zhiyu Wang 001; Hua Chen 003; Jiarui Liu 001; Faxin Yu (IEICE Electron. Express, 2021)

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC. - Yu Liu; Mingliang Chen; Chenge Wang; Jiarui Liu 001; Zhiyu Wang 001; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2022)

A 14-Bit 3-GS/s DAC Achieving SFDR >63dB Up to 1.4GHz With Random Differential-Quad Switching Technique. - Fengjie Wang; Zhiyu Wang 001; Jiarui Liu 001; Faxin Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Low Phase Noise VCO With Placement Reordered Cores and High-Q Bond Wire Array Inductors. - Faxin Yu; Jiahao Chen; Haoming Li 004; Tengjia Wang; Yao Yang; Wenfang Xiong; Zhiyu Wang 001; Jiarui Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Frequency-Domain I/Q Imbalance Calibration Algorithm for Wideband Direct Conversion Receivers Using Low-Cost Compensator. - Xiaoye Peng; Faxin Yu; Zhiyu Wang 001; Jiarui Liu 001; Chenge Wang; Jing Wang (IEEE Access, 2023)

An enhanced peak limited digital predistortion based on indirect learning architecture. - Guojing Huang; Zhiyu Wang 001; Jiarui Liu 001; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2023)

A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA. - Yaguang Song; Yilun Wang; Jiarui Liu 001; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2023)

Multi-chip phase synchronization circuit of fractional-N PLL. - Yantian Xu; Zhiyu Wang 001; Jiarui Liu 001; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2023)

A low-fractional-spur fractional-N PLL using a probability-distribution-shaping delta-sigma modulator. - Yao Yang; Faxin Yu; Haoming Li 004; Jiahao Chen; Tengjia Wang; Yu Liu; Hua Chen 003; Jiarui Liu 001 (IEICE Electron. Express, 2025)

A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. - Yu Liu; Yupeng Shen; Mingliang Chen; Hui Xu; Xubin Chen; Jiarui Liu 001; Zhiyu Wang 001; Faxin Yu (IEEE Trans. Very Large Scale Integr. Syst., 2025)