A 3D Tiled Low Power Accelerator for Convolutional Neural Network. - Yuxiang Huan; Jiawei Xu 002; Lirong Zheng 001; Hannu Tenhunen; Zhuo Zou (ISCAS, 2018)

A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks. - Jiawei Xu 002; Yuxiang Huan; Li-Rong Zheng 001; Zhuo Zou (SoCC, 2018)

Optimized Near-Zero Quantization Method for Flexible Memristor Based Neural Network. - Jiawei Xu 002; Yuxiang Huan; Kunlong Yang; Yiqiang Zhan; Zhuo Zou; Li-Rong Zheng 001 (IEEE Access, 2018)

Universal and Convenient Optimization Strategies for Three-Terminal Memristors. - Kunlong Yang; Yuxiang Huan; Jiawei Xu 002; Zhuo Zou; Yiqiang Zhan; Li-Rong Zheng 001; Fernando Seoane (IEEE Access, 2018)

Energy-Aware Workload Allocation for Distributed Deep Neural Networks in Edge-Cloud Continuum. - Yi Jin 007; Jiawei Xu 002; Yuxiang Huan; Yulong Yan; Lirong Zheng 001; Zhuo Zou (SoCC, 2019)

A Smart Dental Health-IoT Platform Based on Intelligent Hardware, Deep Learning, and Mobile Terminal. - Lizheng Liu; Jiawei Xu 002; Yuxiang Huan; Zhuo Zou; Shih-Ching Yeh; Lirong Zheng 001 (IEEE J. Biomed. Health Informatics, 2020)

Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks. - Jiawei Xu 002; Yuxiang Huan; Yi Jin 007; Haoming Chu; Li-Rong Zheng 001; Zhuo Zou (J. Signal Process. Syst., 2020)

A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. - Jiawei Xu 002; Deyu Wang; Feng Li 051; Lianhao Zhang; Dimitrios Stathis 001; Yu Yang; Yi Jin 007; Anders Lansner; Ahmed Hemani; Zhuo Zou; Li-Rong Zheng 001 (AICAS, 2021)

Self-aware distributed deep learning framework for heterogeneous IoT edge devices. - Yi Jin 007; Jiawei Cai; Jiawei Xu 002; Yuxiang Huan; Yulong Yan; Bin Huang; Yongliang Guo; Lirong Zheng 001; Zhuo Zou (Future Gener. Comput. Syst., 2021)

IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm² Area Efficiency. - Boming Huang; Yuxiang Huan; Haoming Chu; Jiawei Xu 002; Lizheng Liu; Lirong Zheng 001; Zhuo Zou (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture. - Jiawei Xu 002; Yuxiang Huan; Boming Huang; Haoming Chu; Yi Jin 007; Li-Rong Zheng 001; Zhuo Zou (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Memristor-Based In-Circuit Computation for Trace-Based STDP. - Deyu Wang; Jiawei Xu 002; Feng Li 051; Lianhao Zhang; Yuning Wang; Anders Lansner; Ahmed Hemani; Lirong Zheng 001; Zhuo Zou (AICAS, 2022)

Edge-Based Collaborative Training System for Artificial Intelligence-of-Things. - Yi Jin 007; Bin Huang; Yulong Yan; Yuxiang Huan; Jiawei Xu 002; Shancang Li; Prosanta Gope 001; Li Da Xu; Zhuo Zou; Lirong Zheng 001 (IEEE Trans. Ind. Informatics, 2022)

Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks. - Jiawei Xu 002; Yi Zheng; Chenxu Sheng; Yichen Cai 003; Dimitrios Stathis 001; Ruisi Shen; Lirong Zheng 001; Zhuo Zou; Laigui Hu; Ahmed Hemani (NEWCAS, 2023)

A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning. - Deyu Wang; Jiawei Xu 002; Feng Li 051; Lianhao Zhang; Chengwei Cao; Dimitrios Stathis 001; Anders Lansner; Ahmed Hemani; Lirong Zheng 001; Zhuo Zou (IEEE Trans. Biomed. Circuits Syst., 2023)

ASLog: An Area-Efficient CNN Accelerator for Per-Channel Logarithmic Post-Training Quantization. - Jiawei Xu 002; Jiangshan Fan; Baolin Nan; Chen Ding; Lirong Zheng 001; Zhuo Zou; Yuxiang Huan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FPGA-Based HPC for Associative Memory System. - Deyu Wang; Yuning Wang; Yu Yang; Dimitrios Stathis 001; Ahmed Hemani; Anders Lansner; Jiawei Xu 002; Li-Rong Zheng 001; Zhuo Zou (ASPDAC, 2024)

Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning. - Jiawei Xu 002; Yi Zheng; Feng Li 051; Dimitrios Stathis 001; Ruisi Shen; Haoming Chu; Anders Lansner; Lirong Zheng 001; Zhuo Zou; Ahmed Hemani (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Scalable Multi-FPGA HPC Architecture for Associative Memory System. - Deyu Wang; Xiaoze Yan; Yu Yang; Dimitrios Stathis 001; Ahmed Hemani; Anders Lansner; Jiawei Xu 002; Li-Rong Zheng 001; Zhuo Zou (IEEE Trans. Biomed. Circuits Syst., 2025)