Scaling Up Physical Design: Challenges and Opportunities. - Guojie Luo; Wentai Zhang 001; Jiaxi Zhang 001; Jason Cong (ISPD, 2016)

Search space reduction for the non-exact projective NPNP Boolean matching problem. - Feng Wang 046; Jiaxi Zhang 001; Lange Wu; Wentai Zhang 001; Guojie Luo (ISCAS, 2017)

BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only). - Minghua Shen; Jiaxi Zhang 001; Nong Xiao 001; Guojie Luo (FPGA, 2018)

Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only). - Wentai Zhang 001; Jiaxi Zhang 001; Minghua Shen; Nong Xiao 001; Guojie Luo (FPGA, 2018)

Adaptive-precision framework for SGD using deep Q-learning. - Wentai Zhang 001; Hanxian Huang; Jiaxi Zhang 001; Ming Jiang 001; Guojie Luo (ICCAD, 2018)

Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Peng Huang 004; Jinfeng Kang (ASAP, 2019)

An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures. - Wentai Zhang 001; Jiaxi Zhang 001; Minghua Shen; Guojie Luo; Nong Xiao 001 (DATE, 2019)

Frequency Improvement of Systolic Array-Based CNNs on FPGAs. - Jiaxi Zhang 001; Wentai Zhang 001; Guojie Luo; Xuechao Wei; Yun Liang 001; Jason Cong (ISCAS, 2019)

Dual-Output LUT Merging during FPGA Technology Mapping. - Feng Wang 046; Liren Zhu; Jiaxi Zhang 001; Lei Li; Yang Zhang; Guojie Luo (ICCAD, 2020)

Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping. - Yijiang Guo; Jiarui Wang; Jiaxi Zhang 001; Guojie Luo (DAC, 2021)

Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning. - Jiaxi Zhang 001; Liwei Ni; Shenggen Zheng; Hao Liu; Xiangfu Zou; Feng Wang 046; Guojie Luo (ICCAD, 2021)

An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode. - Jiaxi Zhang 001; Tao Yang 031; Qingzheng Li; Bo Zhou; Yang Yang; Guojie Luo; Jianping Shi (ISCAS, 2021)

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Jinfeng Kang; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). - Jiaxi Zhang 001; Qiuyang Gao; Yijiang Guo; Bizhao Shi; Guojie Luo (ASP-DAC, 2022)

Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks. - Yijiang Guo; Xinming Wei; Jiaxi Zhang 001; Guojie Luo (ICCD, 2022)

GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs. - Xinming Wei; Jiaxi Zhang 001; Guojie Luo (DAC, 2023)

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. - Jiaxi Zhang 001; Shenggen Zheng; Liwei Ni; Huawei Li 001; Guojie Luo (DATE, 2023)

Fast Exact NPN Classification with Influence-Aided Canonical Form. - Yonghe Zhang; Liwei Ni; Jiaxi Zhang 001; Guojie Luo; Huawei Li 001; Shenggen Zheng (ICCAD, 2023)

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. - Liwei Ni; Zonglin Yang; Jiaxi Zhang 001; Junfeng Liu; Huawei Li 001; Biwei Xie; Xinquan Li (ICCD, 2023)

Automated Design of Chiplets. - Alberto L. Sangiovanni-Vincentelli; Zheng Liang 003; Zhe Zhou 002; Jiaxi Zhang 001 (ISPD, 2023)

MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA. - Liwei Ni; Zonglin Yang; Jiaxi Zhang 001; Changhong Feng; Jianhua Liu; Guojie Luo; Huawei Li 001; Biwei Xie; Xingquan Li (CoRR, 2023)

PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs. - Tao Yang 031; Dongyue Li; Fei Ma; Zhuoran Song; Yilong Zhao; Jiaxi Zhang 001; Fangxin Liu; Li Jiang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. - Bizhao Shi; Jiaxi Zhang 001; Zhuolun He; Xuechao Wei; Sicheng Li 001; Guojie Luo; Hongzhong Zheng; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SpecPIM: Accelerating Speculative Inference on PIM-Enabled System via Architecture-Dataflow Co-Exploration. - Cong Li; Zhe Zhou 002; Size Zheng 001; Jiaxi Zhang 001; Yun Liang 001; Guangyu Sun 003 (ASPLOS (3), 2024)

PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. - Bizhao Shi; Tuo Dai; Jiaxi Zhang 001; Xuechao Wei; Guojie Luo (DAC, 2024)

BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (DATE, 2024)

Incremental SAT-based Exact Synthesis. - Sunan Zou; Jiaxi Zhang 001; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2024)

AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration. - Xinming Wei; Ziyun Zhang; Sunan Zou; Kaiwen Sun; Jiahao Zhang; Jiaxi Zhang 001; Ping Fan; Guojie Luo (ICCAD, 2024)

Rethinking IC Layout Vulnerability: Simulation-Based Hardware Trojan Threat Assessment with High Fidelity. - Xinming Wei; Jiaxi Zhang 001; Guojie Luo (SP, 2024)

VerilogReader: LLM-Aided Hardware Test Generation. - Ruiyang Ma; Yuxin Yang; Ziqian Liu; Jiaxi Zhang 001; Min Li 019; Junhua Huang; Guojie Luo (CoRR, 2024)

PowerSyn: A Logic Synthesis Framework With Early Power Optimization. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Bridging the Gap between Hardware Fuzzing and Industrial Verification. - Ruiyang Ma; Tianhao Wei; Jiaxi Zhang 001; Chun Yang; Jiangfang Yi; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2025)