A 0.029MM2 17-FJ/Conv.-Step CT $ Delta Sigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer. - Jiaxin Liu 001; Shaolan Li; Wenjuan Guo; Guangjun Wen; Nan Sun 001 (VLSI Circuits, 2018)

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. - Dengquan Li; Jiaxin Liu 001; Haoyu Zhuang; Zhangming Zhu; Yintang Yang; Nan Sun 001 (CICC, 2019)

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. - Xiyuan Tang; Shaolan Li; Linxiao Shen; Wenda Zhao 002; Xiangxing Yang; Randy Williams; Jiaxin Liu 001; Zhichao Tan; Neal A. Hall; Nan Sun 001 (ISSCC, 2019)

A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer. - Jiaxin Liu 001; Shaolan Li; Wenjuan Guo; Guangjun Wen; Nan Sun 001 (IEEE J. Solid State Circuits, 2019)

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting. - Haoyu Zhuang; Wenjuan Guo; Jiaxin Liu 001; He Tang 003; Zhangming Zhu; Long Chen 004; Nan Sun 001 (IEEE J. Solid State Circuits, 2019)

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. - Jiaxin Liu 001; Chen-Kai Hsu; Xiyuan Tang; Shaolan Li; Guangjun Wen; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture. - Haoyu Zhuang; Jiaxin Liu 001; Nan Sun 001 (CICC, 2020)

16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. - Jiaxin Liu 001; Xiyuan Tang; Wenda Zhao 002; Linxiao Shen; Nan Sun 001 (ISSCC, 2020)

9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. - Jiaxin Liu 001; Xing Wang; Zijie Gao; Mingtao Zhan; Xiyuan Tang; Nan Sun 001 (ISSCC, 2020)

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao 002; Chen-Kai Hsu; Jiaxin Liu 001; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2020)

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration. - Dengquan Li; Zhangming Zhu; Jiaxin Liu 001; Haoyu Zhuang; Yintang Yang; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation. - Jiaxin Liu 001; Xiyuan Tang; Wenda Zhao 002; Linxiao Shen; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. - Xiyuan Tang; Shaolan Li; Xiangxing Yang; Linxiao Shen; Wenda Zhao 002; Randall P. Williams; Jiaxin Liu 001; Zhichao Tan; Neal A. Hall; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao 002; Chen-Kai Hsu; Jiaxin Liu 001; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; Shaolan Li; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. - Xiaodan Zhou; Zehao Li; Yujie Wang; Xiong Zhou; Shiheng Yang; Jiaxin Liu 001; Qiang Li 021 (APCCAS, 2021)

A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. - Yan Zeng; Shiheng Yang; Yueduo Liu; Zehao Li; Wengang Huang; Xiaozong Huang; Xiong Zhou; Jiaxin Liu 001; Qiang Li 021 (A-SSCC, 2021)

An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. - Yi Zhong 002; Xiyuan Tang; Jiaxin Liu 001; Wenda Zhao 002; Shaolan Li; Nan Sun 001 (CICC, 2021)

A Low-Power RC Oscillator with Offset and Path Delay Cancellation. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Shiheng Yang; Jiaxin Liu 001; Xiong Zhou; Qiang Li 021 (ICTA, 2021)

27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering. - Jiaxin Liu 001; Dengquan Li; Yi Zhong 002; Xiyuan Tang; Nan Sun 001 (ISSCC, 2021)

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. - Wei Shi 011; Jiaxin Liu 001; Abhishek Mukherjee; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Wenda Zhao 002; Nan Sun 001 (ISSCC, 2021)

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. - Xiyuan Tang; Xiangxing Yang; Jiaxin Liu 001; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu 001; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. - Chen-Kai Hsu; Xiyuan Tang; Jiaxin Liu 001; Rui Xu 008; Wenda Zhao 002; Abhishek Mukherjee; Timothy R. Andeen; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. - Jiaxin Liu 001; Xing Wang; Zijie Gao; Mingtao Zhan; Xiyuan Tang; Chen-Kai Hsu; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC. - Haoyu Zhuang; Jiaxin Liu 001; He Tang 004; Xizhu Peng; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS. - Mingkang Zhang; Zihao Zhu; Yueduo Liu; Zehao Zhang; Rongxin Bao; Jiahui Lin; Haovu Zhuang; Jiaxin Liu 001; Xiong Zhou; Shiheng Yang; Qiang Li 021 (ICTA, 2022)

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. - Guodong Yin; Mufeng Zhou; Yiming Chen; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu 001; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (CoRR, 2022)

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. - Xiyuan Tang; Jiaxin Liu 001; Yi Shen 007; Shaolan Li; Linxiao Shen; Arindam Sanyal; Kareem Ragab; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. - Zehao Zhang; Shiheng Yang; Yueduo Liu; Zihao Zhu; Jiahui Lin; Rongxin Bao; Tailong Xu; Zhizhan Yang; Mingkang Zhang; Jiaxin Liu 001; Xiong Zhou; Jun Yin 001; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. - Yiming Chen; Guodong Yin; Mufeng Zhou; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu 001; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. - Xiyuan Tang; Xiangxing Yang; Jiaxin Liu 001; Zongnan Wang; Wei Shi 011; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping. - Tiange Yi; Zhenbing Li; Bing Du; Shiheng Yang; Jiaxin Liu 001 (ICTA, 2024)

Mitigating Sampling Noise for Energy-Efficient ADCs: A Tutorial Brief. - Chang Liu; Jiaxin Liu 001; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 003; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu 001; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C. - Yueduo Liu; Zihao Zhu; Xinyu Yang; Rongxin Bao; Zehao Zhang; Hongshuai Zhang; Jiaxin Liu 001; Zheng Wang 050; Mingkang Zhang; Na Yan; Jun Yin 001; Pui-In Mak; et al. (ISSCC, 2025)

18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW. - Han Zhao; Xuanhao Zhang; Qijin Deng; Jialin Hu; Zhenbing Li; Shiheng Yang; Jiaxin Liu 001 (ISSCC, 2025)

Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL. - Jingrun Song; Xinyu Yang; Jiaxu Liu; Yueduo Liu; Zihao Zhu; Zhengxuan Han; Zehao Zhang; Jiaxin Liu 001; Hongshuai Zhang; Jun Yin 001; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling. - Xuanhao Zhang; Jialin Hu; Xingshuai Zou; Shiheng Yang; Jiaxin Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 3.6mW 5MS/s 100dB-SNDR 2-Step SAR ADC with Continuous-Time Second-Stage and Tracking Averaging. - Congyu Jin; Zhaoyang Shen; Xingshuai Zou; Xuanhao Zhang; Han Zhao; Zhong Zhang; Ning Ning; Hongshuai Zhang; Zheng Wang 050; Zhenbing Li; Shiheng Yang; Xiangyu Mao; et al. (CICC, 2026)

A 30kHz-BW 100.6dB-SNDR ΔΣ Modulator with Swapped Sampling-Feedback Operation and Optimized kT/C Noise Cancellation. - Xuanhao Zhang; Han Zhao; Congyu Jin; Hongshuai Zhang; Zheng Wang 050; Zhong Zhang; Ning Ning; Zhenbing Li; Xiangyu Mao; Shiheng Yang; Jiaxin Liu 001 (CICC, 2026)