An SDRAM controller optimized for high definition video coding application. - Jiayi Zhu 001; Peilin Liu; Dajiang Zhou (ISCAS, 2008)

Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder. - Xianmin Chen; Peilin Liu; Jiayi Zhu 001; Dajiang Zhou; Satoshi Goto (ISCAS, 2009)

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. - Dajiang Zhou; Jinjia Zhou; Jiayi Zhu 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. - Xianmin Chen; Peilin Liu; Dajiang Zhou; Jiayi Zhu 001; Xingguang Pan; Satoshi Goto (IEICE Trans. Electron., 2010)

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. - Dajiang Zhou; Jinjia Zhou; Xun He; Jiayi Zhu 001; Ji Kong; Peilin Liu; Satoshi Goto (IEEE J. Solid State Circuits, 2011)

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. - Dajiang Zhou; Jinjia Zhou; Jiayi Zhu 001; Peilin Liu; Satoshi Goto (ISSCC, 2012)

A combined SAO and de-blocking filter architecture for HEVC video decoder. - Jiayi Zhu 001; Dajiang Zhou; Gang He 002; Satoshi Goto (ICIP, 2013)

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder. - Jiayi Zhu 001; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Fast SAO estimation algorithm and its VLSI architecture. - Jiayi Zhu 001; Dajiang Zhou; Shinji Kimura; Satoshi Goto (ICIP, 2014)

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. - Heming Sun; Dajiang Zhou; Jiayi Zhu 001; Shinji Kimura; Satoshi Goto (VCIP, 2014)

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. - Jiayi Zhu 001; Dajiang Zhou; Shinji Kimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

An independent bandwidth reduction device for HEVC VLSI video system. - Jiayi Zhu 001; Li Guo 006; Dajiang Zhou; Shinji Kimura; Satoshi Goto (ISCAS, 2015)

A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. - Jinjia Zhou; Dajiang Zhou; Jiayi Zhu 001; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2015)

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. - Dajiang Zhou; Shihao Wang; Heming Sun; Jian-Bin Zhou; Jiayi Zhu 001; Yijin Zhao; Jinjia Zhou; Shuping Zhang; Shinji Kimura; Takeshi Yoshimura; Satoshi Goto (ISSCC, 2016)

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. - Dajiang Zhou; Shihao Wang; Heming Sun; Jian-Bin Zhou; Jiayi Zhu 001; Yijin Zhao; Jinjia Zhou; Shuping Zhang; Shinji Kimura; Takeshi Yoshimura; Satoshi Goto (IEEE J. Solid State Circuits, 2017)