Generation of efficient bitstreams for functional tests of video decoders. - Soonwoo Choi; Seunggyu Jeoung; Jicheon Kim; Soo-Ik Chae (ICCE, 2013)

Efficient test bitstream generation with an N-way covering algorithm for configurations of high-level syntax elements in video decoders. - Soonwoo Choi; Jicheon Kim; Soo-Ik Chae (IEEE Trans. Consumer Electron., 2013)

Live Demonstration: Layer-wise Configurable CNN Accelerator with High PE Utilization. - Chunmyung Park; Eunjae Hyun; Jicheon Kim; Xuan Truong Nguyen; Hyuk-Jae Lee (ISCAS, 2023)

A Scalable Multi-Chip YOLO Accelerator With a Lightweight Inter-Chip Adapter. - Jicheon Kim; Chunmyung Park; Eunjae Hyun; Xuan Truong Nguyen; Hyuk-Jae Lee (ISCAS, 2024)

A Highly-Scalable Deep-Learning Accelerator With a Cost-Effective Chip-to-Chip Adapter and a C2C-Communication-Aware Scheduler. - Jicheon Kim; Chunmyung Park; Eunjae Hyun; Xuan Truong Nguyen; Hyuk-Jae Lee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

Leveraging Hot Data in a Multi-Tenant Accelerator for Effective Shared Memory Management. - Chunmyung Park; Jicheon Kim; Eunjae Hyun; Xuan Truong Nguyen; Hyuk-Jae Lee (DATE, 2025)

A Multi-Chip-Module-Based Architecture Simulator for Scaling Vision Transformer Inference. - Jicheon Kim (ICCE, 2025)

Live Demonstration: A Scalable CNN Accelerator SoC With a Cost-Effective Chip-to-Chip Adapter. - Jicheon Kim; Chunmyung Park; Eunjae Hyun; Xuan Truong Nguyen; Hyuk-Jae Lee (ISCAS, 2025)