Converting sequential iterative algorithms to recurrent equations for automatic design of systolic arrays. - Jichun Bu; Ed F. Deprettere (ICASSP, 1988)

A VLSI system architecture for high-speed radiative transfer 3D image synthesis. - Jichun Bu; Ed F. Deprettere (Vis. Comput., 1989)

A design methodology for fixed-size systolic arrays. - Jichun Bu; Ed F. Deprettere; Patrick M. Dewilde (ASAP, 1990)

Systolic array implementation of nested loop programs. - Jichun Bu; Ed F. Deprettere; Lothar Thiele (ASAP, 1990)

Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms. - Alfons A. J. de Lange; Ed F. Deprettere; Alle-Jan van der Veen; Jichun Bu (ICASSP, 1990)

Processor clustering for the design of optimal fixed-size systolic arrays. - Jichun Bu; Ed F. Deprettere (ASAP, 1991)

A parallel system for photo realistic artificial scene rendering. - Ed F. Deprettere; Gerben J. Hekstra; Li-Sheng Shen; Jichun Bu; Gerrit Boersma (ASAP, 1994)

Design of a hybrid reconfigurable coprocessor. - Xiang Wang; Su Zhang; Wei Ni; Yukun Song; Yanhui Yang; Jichun Bu (ASICON, 2013)

A Hybrid Reconfigurable System for Parallel and Intensive Computation. - Wei Ni; Xiang Wang; Su Zhang; Yukun Song; Yanhui Yang; Jichun Bu (HPCC/EUC, 2013)