Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster. - Jie Chen 042; Igor Loi; Luca Benini; Davide Rossi (DATE, 2020)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (CoRR, 2023)

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. - Jie Chen 042; Igor Loi; Eric Flamand; Giuseppe Tagliavini; Luca Benini; Davide Rossi (IEEE Trans. Very Large Scale Integr. Syst., 2023)