Jie Gu
Orcid: 0000-0003-2912-7294Affiliations:
- Northwestern University, Evanston, IL, USA
According to our database1,
Jie Gu
authored at least 48 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance.
IEEE J. Solid State Circuits, 2023
Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Human emotion based real-time memory and computation management on resource-limited edge devices.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier.
IEEE J. Solid State Circuits, 2021
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique.
IEEE J. Solid State Circuits, 2021
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing.
IEEE J. Solid State Circuits, 2021
IACR Cryptol. ePrint Arch., 2021
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture.
IEEE J. Solid State Circuits, 2020
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor.
IEEE J. Solid State Circuits, 2019
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation.
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications.
IEEE J. Solid State Circuits, 2018
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion.
Proceedings of the International Conference on Computer-Aided Design, 2018
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Compiler-guided instruction-level clock scheduling for timing speculative processors.
Proceedings of the 55th Annual Design Automation Conference, 2018
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks.
IACR Cryptol. ePrint Arch., 2017
(Invited) Software-guided greybox design methodology with integrated power and clock management.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Exploration of associative power management with instruction governed operation for ultra-low power design.
Proceedings of the 53rd Annual Design Automation Conference, 2016