Exploration of associative power management with instruction governed operation for ultra-low power design. - Tianyu Jia; Yuanbo Fan; Russ Joseph; Jie Gu 001 (DAC, 2016)

Analysis and Design of Energy Efficient Time Domain Signal Processing. - Zhengyu Chen 002; Jie Gu 001 (ISLPED, 2016)

Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design. - Huanyu Wang; Geng Xie; Jie Gu 001 (ISLPED, 2016)

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. - Tianyu Jia; Russ Joseph; Jie Gu 001 (DAC, 2017)

Memristor-Based Clock Design and Optimization with In-Situ Tunability. - Shuyu Kong; Jie Gu 001; Hai Zhou 001 (ISVLSI, 2017)

(Invited) Software-guided greybox design methodology with integrated power and clock management. - Tianyu Jia; Yuanbo Fan; Russ Joseph; Jie Gu 001 (MWSCAS, 2017)

Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks. - Amin Rezaei 001; Yuanqi Shen; Shuyu Kong; Jie Gu 001; Hai Zhou 001 (IACR Cryptol. ePrint Arch., 2017)

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. - Zhengyu Chen 002; Jie Gu 001 (A-SSCC, 2018)

A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. - Tianyu Jia; Jie Gu 001 (A-SSCC, 2018)

Compiler-guided instruction-level clock scheduling for timing speculative processors. - Yuanbo Fan; Tianyu Jia; Jie Gu 001; Simone Campanoni; Russ Joseph (DAC, 2018)

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. - Tianyu Jia; Russ Joseph; Jie Gu 001 (ESSCIRC, 2018)

Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. - Kofi Otseidu; Tianyu Jia; Joshua Bryne; Levi J. Hargrove; Jie Gu 001 (ICCAD, 2018)

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. - Zhengyu Chen 002; Hai Zhou 001; Jie Gu 001 (ICCD, 2018)

Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. - Josiah D. Hester; Tianyu Jia; Jie Gu 001 (SoCC, 2018)

A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications. - Tianyu Jia; Jie Gu 001 (IEEE J. Solid State Circuits, 2018)

A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. - Zhengyu Chen 002; Huanyu Wang; Geng Xie; Jie Gu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design. - Shuyu Kong; Hai Zhou 001; Jie Gu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. - Zhengyu Chen 002; Hai Zhou 001; Jie Gu 001 (DAC, 2019)

A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. - Zhengyu Chen 002; Jie Gu 001 (ISSCC, 2019)

An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. - Tianyu Jia; Russ Joseph; Jie Gu 001 (ISSCC, 2019)

Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. - Amin Rezaei 001; Jie Gu 001; Hi Zhou (ISVLSI, 2019)

A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. - Zhengyu Chen 002; Jie Gu 001 (IEEE J. Solid State Circuits, 2019)

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. - Tianyu Jia; Russ Joseph; Jie Gu 001 (IEEE J. Solid State Circuits, 2019)

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. - Zhengyu Chen 002; Hai Zhou 001; Jie Gu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training. - Yijie Wei; Qiankai Cao; Jie Gu 001; Kofi Otseidu; Levi J. Hargrove (CICC, 2020)

Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC. - Yijie Wei; Kofi Otseidu; Jie Gu 001 (DAC, 2020)

A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication. - Yijie Wei; Qiankai Cao; Levi J. Hargrove; Jie Gu 001 (EMBC, 2020)

31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. - Tianyu Jia; Yuhao Ju; Jie Gu 001 (ISSCC, 2020)

NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. - Tianyu Jia; Yuhao Ju; Russ Joseph; Jie Gu 001 (MICRO, 2020)

A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. - Zhengyu Chen 002; Sihua Fu; Qiankai Cao; Jie Gu 001 (VLSI Circuits, 2020)

An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. - Tianyu Jia; Yijie Wei; Russ Joseph; Jie Gu 001 (IEEE J. Solid State Circuits, 2020)

15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. - Zhengyu Chen 002; Xi Chen 099; Jie Gu 001 (ISSCC, 2021)

Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. - Amin Rezaei 001; Jie Gu 001; Hai Zhou 001 (IACR Cryptol. ePrint Arch., 2021)

High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. - Zhengyu Chen 002; Jie Gu 001 (IEEE J. Solid State Circuits, 2021)

A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. - Tianyu Jia; Yuhao Ju; Jie Gu 001 (IEEE J. Solid State Circuits, 2021)

A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier. - Yijie Wei; Qiankai Cao; Kofi Otseidu; Levi J. Hargrove; Jie Gu 001 (IEEE J. Solid State Circuits, 2021)

A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition. - Yijie Wei; Xi Chen 099; Jie Gu 001 (CICC, 2022)

Human emotion based real-time memory and computation management on resource-limited edge devices. - Yijie Wei; Zhiwei Zhong; Jie Gu 001 (DAC, 2022)

A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. - Yuhao Ju; Shiyu Guo; Zixuan Liu; Tianyu Jia; Jie Gu 001 (ESSCIRC, 2022)

A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance. - Yuhao Ju; Jie Gu 001 (ISSCC, 2022)

A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management. - Qiankai Cao; Jie Gu 001 (VLSI Technology and Circuits, 2022)

A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. - Xi Chen 099; Aly Shoukry; Tianyu Jia; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (CICC, 2023)

Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning. - Qiankai Cao; Xi Chen 099; Jie Gu 001 (ISLPED, 2023)

Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs. - Xi Chen 099; Jiaxiang Feng; Aly Shoukry; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (VLSI Technology and Circuits, 2023)

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality. - Yuhao Ju; Yijie Wei; Xi Chen 099; Jie Gu 001 (VLSI Technology and Circuits, 2023)

Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration. - Yijie Wei; Xi Chen 099; Jie Gu 001 (VLSI Technology and Circuits, 2023)

A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance. - Yuhao Ju; Jie Gu 001 (IEEE J. Solid State Circuits, 2023)

LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices. - Shiyu Guo; Yuhao Ju; Xi Chen 099; Jie Gu 001 (DAC, 2024)

20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices. - Yuhao Ju; Ganqi Xu; Jie Gu 001 (ISSCC, 2024)

33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture. - Zhiwei Zhong; Yijie Wei; Lance Christopher Go; Jie Gu 001 (ISSCC, 2024)

Software-Hardware Codesign of Ray-Tracing Accelerator for Edge AR/VR With Viewpoint-Focused 3D Construction and Efficient Data Structure. - Shiyu Guo; Sachin S. Sapatnekar; Jie Gu 001 (MWSCAS, 2024)

Scalable Physics-Embedded Neural Networks for Real-Time Robotic Control in Embedded Systems. - Zhiwei Zhong; Yuhao Ju; Jie Gu 001 (MWSCAS, 2024)

A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics. - Qiankai Cao; Juin Chuen Oh; Jie Gu 001 (VLSI Technology and Circuits, 2024)

Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics. - Qiankai Cao; Yiqi Li; Juin Chuen Oh; Jie Gu 001 (ASP-DAC, 2025)

Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications. - Zhiwei Zhong; Yijie Wei; Lance Christopher Go; Yiqi Li; Jie Gu 001 (ASP-DAC, 2025)

Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots. - Qiankai Cao; Yuhao Ju; Zhiwei Zhong; Zhengyu Chen 002; Jie Gu 001 (ACM Great Lakes Symposium on VLSI, 2025)

Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering. - Shiyu Guo; Yuhao Ju; Xi Chen 099; Sachin S. Sapatnekar; Jie Gu 001 (IEEE J. Solid State Circuits, 2025)

A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics. - Qiankai Cao; Juin Chuen Oh; Jie Gu 001 (IEEE J. Solid State Circuits, 2025)

A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks. - Yuhao Ju; Yijie Wei; Jie Gu 001 (IEEE J. Solid State Circuits, 2025)

A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors. - Xi Chen 099; Jiaxiang Feng; Aly Shoukry; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (IEEE J. Solid State Circuits, 2025)