Employing Compilers for Determining Architectural Features of Application-Specific DSPs. - Jie Guo 007; Michael Hosemann; Gerhard P. Fettweis (PARELEC, 2004)

A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware. - Jie Guo 007; Gleb Belov; Gerhard P. Fettweis (ARC, 2006)

Code Generation for STA Architecture. - Jie Guo 007; Torsten Limberg; Emil Matús; Björn Mennenga; Reimund Klemm; Gerhard P. Fettweis (Euro-Par, 2006)

A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation. - Jie Guo 007; Jun Liu; Björn Mennenga; Gerhard P. Fettweis (ASAP, 2007)

Integrated code generation by using fuzzy control system. - Xiaoyan Jia; Jie Guo 007; Gerhard P. Fettweis (SCOPES, 2008)

Approaches to code generation for synchronous transfer architecture (STA). - Jie Guo 007 (2008)