On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits. - Pieter Jonker; Jie Han 001 (CAMP, 2000)

A Study on Fault-Tolerant Circuits Using Redundancy. - Jie Han 001; Pieter Jonker (VLSI, 2003)

From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers. - Jie Han 001; Pieter Jonker (ICPR (3), 2004)

Faults, Error Bounds and Reliability of Nanoelectronic Circuits. - Jie Han 001; Erin Taylor 001; Jianbo Gao; José A. B. Fortes (ASAP, 2005)

Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics. - Jie Han 001; Jianbo Gao; Yan Qi 003; Pieter Jonker; José A. B. Fortes (IEEE Des. Test Comput., 2005)

Stochastic computational models for accurate reliability evaluation of logic circuits. - Hao Chen; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2010)

A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits. - Hao Chen; Jie Han 001; Fabrizio Lombardi (DFT, 2011)

On the Reliable Performance of Sequential Adders for Soft Computing. - Jinghang Liang; Jie Han 001; Fabrizio Lombardi (DFT, 2011)

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS. - Nachiket Rajderkar; Marco Ottavi; Salvatore Pontarelli; Jie Han 001; Fabrizio Lombardi (DFT, 2011)

A hybrid memory cell using Single-Electron transfer. - Wei Wei 034; Jie Han 001; Fabrizio Lombardi (NANOARCH, 2011)

Reliability evaluation of logic circuits using probabilistic gate models. - Jie Han 001; Hao Chen; Erin Boykin; José A. B. Fortes (Microelectron. Reliab., 2011)

Hardening a memory cell for low power operation by gate leakage reduction. - Jianping Gong; Yong-Bin Kim; Fabrizio Lombardi; Jie Han 001 (DFT, 2012)

Modeling a single electron turnstile in HSPICE. - Fabrizio Lombardi; Wei Wei 034; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2012)

Macromodeling a phase change memory (PCM) cell by HSPICE. - Pilin Junsangsri; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2012)

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs. - Jinghang Liang; Jie Han 001; Linbin Chen; Fabrizio Lombardi (NANOARCH, 2012)

Cell design and comparative evaluation of a novel 1T memristor-based memory. - Vikas Sakode; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2012)

Stochastic Boolean networks: An efficient approach to modeling gene regulatory networks. - Jinghang Liang; Jie Han 001 (BMC Syst. Biol., 2012)

Approximate computing: An emerging paradigm for energy-efficient design. - Jie Han 001; Michael Orshansky (ETS, 2013)

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration. - Yu Ren; Leibo Liu; Shouyi Yin; Qinghua Wu; Shaojun Wei; Jie Han 001 (ISCAS, 2013)

A PCM-based TCAM cell using NDR. - Hao Wu; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2013)

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration. - Yu Ren; Leibo Liu; Shouyi Yin; Jie Han 001; Qinghua Wu; Shaojun Wei (J. Syst. Archit., 2013)

Analysis of Error Masking and Restoring Properties of Sequential Circuits. - Jinghang Liang; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2013)

New Metrics for the Reliability of Approximate and Probabilistic Adders. - Jinghang Liang; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2013)

A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS. - Jinghang Liang; Zhiyin Zhou; Jie Han 001; Duncan G. Elliott (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction. - Pilin Junsangsri; Fabrizio Lombardi; Jie Han 001 (DATE, 2014)

A low-power, high-performance approximate multiplier with configurable partial error recovery. - Cong Liu 015; Jie Han 001; Fabrizio Lombardi (DATE, 2014)

A system-level scheme for resistance drift tolerance of a multilevel phase change memory. - Pilin Junsangsri; Jie Han 001; Fabrizio Lombardi (DFT, 2014)

FDSOI SRAM cells for low power design at 22nm technology node. - Linbin Chen; Fabrizio Lombardi; Jie Han 001 (MWSCAS, 2014)

An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior. - Linbin Chen; Fabrizio Lombardi; Jie Han 001 (MWSCAS, 2014)

A memristor-based TCAM (Ternary Content Addressable Memory) cell. - Pilin Junsangsri; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2014)

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design. - Pilin Junsangsri; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2014)

Gene perturbation and intervention in context-sensitive stochastic Boolean networks. - Peican Zhu; Jinghang Liang; Jie Han 001 (BMC Syst. Biol., 2014)

Asynchronous Stochastic Boolean Networks as Gene Network Models. - Peican Zhu; Jie Han 001 (J. Comput. Biol., 2014)

Robust HSPICE modeling of a single electron turnstile. - Wei Wei 034; Jie Han 001; Fabrizio Lombardi (Microelectron. J., 2014)

Stochastic Multiple-Valued Gene Networks. - Peican Zhu; Jie Han 001 (IEEE Trans. Biomed. Circuits Syst., 2014)

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation. - Jie Han 001; Hao Chen; Jinghang Liang; Peican Zhu; Zhixi Yang; Fabrizio Lombardi (IEEE Trans. Computers, 2014)

A Stochastic Approach for the Analysis of Fault Trees With Priority AND Gates. - Peican Zhu; Jie Han 001; Leibo Liu; Ming Jian Zuo (IEEE Trans. Reliab., 2014)

Stochastic circuit design and performance evaluation of vector quantization. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (ASAP, 2015)

DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis. - Chen Zou 001; Weikang Qian; Jie Han 001 (ASICON, 2015)

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. - Leibo Liu; Yu Ren; Chenchen Deng; Shouyi Yin; Shaojun Wei; Jie Han 001 (ASP-DAC, 2015)

An approximate voting scheme for reliable computing. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (DATE, 2015)

Minimizing the number of process corner simulations during design verification. - Michael Shoniker; Bruce F. Cockburn; Jie Han 001; Witold Pedrycz (DATE, 2015)

Evaluating the impact of spike and flicker noise in phase change memories. - Salin Junsangsri; Fabrizio Lombardi; Jie Han 001 (DFTS, 2015)

Approximate compressors for error-resilient multiplier design. - Zhixi Yang; Jie Han 001; Fabrizio Lombardi (DFTS, 2015)

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing. - Linbin Chen; Jie Han 001; Weiqiang Liu 001; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2015)

A Comparative Review and Evaluation of Approximate Adders. - Honglan Jiang; Jie Han 001; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2015)

A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM). - Pilin Junsangsri; Fabrizio Lombardi; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2015)

Matrix multiplication by an inexact systolic array. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2015)

Transmission gate-based approximate adders for inexact computing. - Zhixi Yang; Jie Han 001; Fabrizio Lombardi (NANOARCH, 2015)

Design and evaluation of stochastic FIR filters. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (PACRIM, 2015)

A Design Approach for Compressor Based Approximate Multipliers. - Naman Maheshwari; Zhixi Yang; Jie Han 001; Fabrizio Lombardi (VLSID, 2015)

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints. - Chen Wu; Chenchen Deng; Leibo Liu; Shouyi Yin; Jie Han 001; Shaojun Wei (Sci. China Inf. Sci., 2015)

An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders. - Cong Liu 015; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2015)

Design and Analysis of Approximate Compressors for Multiplication. - Amir Momeni; Jie Han 001; Paolo Montuschi; Fabrizio Lombardi (IEEE Trans. Computers, 2015)

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures. - Chen Wu; Chenchen Deng; Leibo Liu; Jie Han 001; Jiqiang Chen; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory. - Pilin Junsangsri; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Multi Scale Comput. Syst., 2015)

A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures. - Peican Zhu; Jie Han 001; Leibo Liu; Fabrizio Lombardi (IEEE Trans. Reliab., 2015)

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. - Yu Ren; Leibo Liu; Shouyi Yin; Jie Han 001; Shaojun Wei (ACM Trans. Reconfigurable Technol. Syst., 2015)

On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ. - Ke Chen 018; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells. - Ke Chen 018; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors. - Jie Han 001; Eugene Leung; Leibo Liu; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures. - Leibo Liu; Chen Wu; Chenchen Deng; Shouyi Yin; Qinghua Wu; Jie Han 001; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A novel gate grading approach for soft error tolerance in combinational circuits. - Mohammad Saeed Ansari; Ali Mahani 001; Jie Han 001; Bruce F. Cockburn (CCECE, 2016)

Design and analysis of an approximate 2D convolver. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (DFT, 2016)

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File. - Salin Junsangsri; Jie Han 001; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2016)

SRAM memory margin probability failure estimation using Gaussian Process regression. - Manish Rana; Ramon Canal; Jie Han 001; Bruce F. Cockburn (ICCD, 2016)

Design and evaluation of an approximate Wallace-Booth multiplier. - Liangyu Qian; Chenghua Wang; Weiqiang Liu 001; Fabrizio Lombardi; Jie Han 001 (ISCAS, 2016)

A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis. - Yuanchang Chen; Xinghua Yang; Fei Qiao; Jie Han 001; Qi Wei 001; Huazhong Yang (ISVLSI, 2016)

Adaptive Filter Design Using Stochastic Circuits. - Honglan Jiang; Chengkun Shen; Pieter P. Jonker; Fabrizio Lombardi; Jie Han 001 (ISVLSI, 2016)

A fully parallel approximate CORDIC design. - Linbin Chen; Fabrizio Lombardi; Jie Han 001; Weiqiang Liu 001 (NANOARCH, 2016)

A comparative evaluation of approximate multipliers. - Honglan Jiang; Cong Liu 015; Naman Maheshwari; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2016)

Introduction to approximate computing. - Jie Han 001 (VTS, 2016)

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. - Pilin Junsangsri; Jie Han 001; Fabrizio Lombardi (Integr., 2016)

Design, evaluation and fault-tolerance analysis of stochastic FIR filters. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (Microelectron. Reliab., 2016)

Reliability and Criticality Analysis of Communication Networks by Stochastic Computation. - Peican Zhu; Jie Han 001; Yangming Guo; Fabrizio Lombardi (IEEE Netw., 2016)

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications. - Linbin Chen; Jie Han 001; Weiqiang Liu 001; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation. - Honglan Jiang; Jie Han 001; Fei Qiao; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation. - Peican Zhu; Jie Han 001; Leibo Liu; Fabrizio Lombardi (IEEE Trans. Reliab., 2016)

Logic-in-Memory With a Nonvolatile Programmable Metallization Cell. - Pilin Junsangsri; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An efficient hardware design for cerebellar models using approximate circuits: special session paper. - Honglan Jiang; Leibo Liu; Jie Han 001 (CODES+ISSS, 2017)

Hardware ODE Solvers using Stochastic Circuits. - Siting Liu 001; Jie Han 001 (DAC, 2017)

Energy efficient stochastic computing with Sobol sequences. - Siting Liu 001; Jie Han 001 (DATE, 2017)

A true random number generator based on parallel STT-MTJs. - Yuanzhuo Qu; Jie Han 001; Bruce F. Cockburn; Witold Pedrycz; Yue Zhang 010; Weisheng Zhao (DATE, 2017)

Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition. - Linbin Chen; Fabrizio Lombardi; Paolo Montuschi; Jie Han 001; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2017)

Evaluating Data Resilience in CNNs from an Approximate Memory Perspective. - Yuanchang Chen; Yizhe Zhu; Fei Qiao; Jie Han 001; Yuansheng Liu; Huazhong Yang (ACM Great Lakes Symposium on VLSI, 2017)

Partially universal modules for high performance logic circuit design. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (MWSCAS, 2017)

Design and operational assessment of an intra-cell hybrid L2 cache. - Linbin Chen; Jie Han 001; Weiqiang Liu 001; Fabrizio Lombardi (NANOARCH, 2017)

A Stochastic Computational Approach for the Analysis of Fuzzy Systems. - Xiaogang Song; Zhengjun Zhai; Peican Zhu; Jie Han 001 (IEEE Access, 2017)

Approximate reliability of multi-state two-terminal networks by stochastic analysis. - Peican Zhu; Yangming Guo; Fabrizio Lombardi; Jie Han 001 (IET Networks, 2017)

A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits. - Honglan Jiang; Cong Liu 015; Leibo Liu; Fabrizio Lombardi; Jie Han 001 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Two Approximate Voting Schemes for Reliable Computing. - Ke Chen 018; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2017)

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing. - Weiqiang Liu 001; Liangyu Qian; Chenghua Wang; Honglan Jiang; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2017)

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC). - Linbin Chen; Jie Han 001; Weiqiang Liu 001; Fabrizio Lombardi (IEEE Trans. Multi Scale Comput. Syst., 2017)

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. - Chen Wu; Chenchen Deng; Leibo Liu; Jie Han 001; Jiqiang Chen; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

Adaptive approximation in arithmetic circuits: A low-power unsigned divider design. - Honglan Jiang; Leibo Liu; Fabrizio Lombardi; Jie Han 001 (DATE, 2018)

An energy-efficient stochastic computational deep belief network. - Yidong Liu; Yanzhi Wang; Fabrizio Lombardi; Jie Han 001 (DATE, 2018)

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks. - Shaahin Angizi; Zhezhi He; Yu Bai 004; Jie Han 001; Mingjie Lin; Ronald F. DeMara; Deliang Fan (ACM Great Lakes Symposium on VLSI, 2018)

Approximate On-chip Memory Optimization Method For Deep Residual Networks. - Xuedi Wang; Zhe Chen; Kaige Jia; Jie Han 001; Qi Wei 001; Fei Qiao; Huazhong Yang (DSP, 2018)

Design and Application of an Approximate 2-D Convolver with Error Compensation. - Ke Chen 018; Jie Han 001; Paolo Montuschi; Weiqiang Liu 001; Fabrizio Lombardi (ISCAS, 2018)

An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing. - Xiaolong Ma; Yipeng Zhang; Geng Yuan; Ao Ren; Zhe Li 001; Jie Han 001; Jingtong Hu; Yanzhi Wang (ISQED, 2018)

A Probabilistic Error Model and Framework for Approximate Booth Multipliers. - Yuying Zhu 003; Weiqiang Liu 001; Jie Han 001; Fabrizio Lombardi (NANOARCH, 2018)

Approximate Arithmetic Circuits and Their Applications. - Jie Han 001 (NOCS, 2018)

Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation. - Peican Zhu; Xiaogang Song; Leibo Liu; Zhen Wang 004; Jie Han 001 (IEEE Access, 2018)

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors. - Mohammad Saeed Ansari; Honglan Jiang; Bruce F. Cockburn; Jie Han 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network. - Yidong Liu; Yanzhi Wang; Fabrizio Lombardi; Jie Han 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A stochastic approach for the reliability evaluation of multi-state systems with dependent components. - Xiaogang Song; Zhengjun Zhai; Yidong Liu; Jie Han 001 (Reliab. Eng. Syst. Saf., 2018)

A Stochastic Computational Multi-Layer Perceptron with Backward Propagation. - Yidong Liu; Siting Liu 001; Yanzhi Wang; Fabrizio Lombardi; Jie Han 001 (IEEE Trans. Computers, 2018)

Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines. - Siting Liu 001; Honglan Jiang; Leibo Liu; Jie Han 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Automatic Selection of Process Corner Simulations for Faster Design Verification. - Michael Shoniker; Oleg Oleynikov; Bruce F. Cockburn; Jie Han 001; Manish Rana; Witold Pedrycz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Design, Evaluation and Application of Approximate High-Radix Dividers. - Linbin Chen; Jie Han 001; Weiqiang Liu 001; Paolo Montuschi; Fabrizio Lombardi (IEEE Trans. Multi Scale Comput. Syst., 2018)

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy. - Yan Li; Yufeng Li 003; Jie Han 001; Jianhao Hu; Fan Yang 001; Xuan Zeng 001; Bruce F. Cockburn; Jie Chen 002 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences. - Siting Liu 001; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Honglan Jiang; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Approximate Arithmetic Circuits: Design and Evaluation. - Honglan Jiang; Leibo Liu; Fabrizio Lombardi; Jie Han 001 (Approximate Circuits, 2019)

Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier. - Shyama Gandhi; Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (CCECE, 2019)

Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression. - Morgan Ledwon; Bruce F. Cockburn; Jie Han 001 (CCECE, 2019)

A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy. - Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (DATE, 2019)

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. - Honglan Jiang; Francisco J. H. Santiago; Mohammad Saeed Ansari; Leibo Liu; Bruce F. Cockburn; Fabrizio Lombardi; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2019)

A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology. - Ruizhe Cai; Ao Ren; Olivia Chen; Ning Liu 007; Caiwen Ding; Xuehai Qian; Jie Han 001; Wenhui Luo; Nobuyuki Yoshikawa; Yanzhi Wang (ISCA, 2019)

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. - Hao Cai 001; Honglan Jiang; Menglin Han; Zhaohao Wang; You Wang 002; Jun Yang 006; Jie Han 001; Leibo Liu; Weisheng Zhao (ISVLSI, 2019)

Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders. - Tingting Zhang; Weiqiang Liu 001; Jie Han 001; Fabrizio Lombardi (NANOARCH, 2019)

A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology. - Ruizhe Cai; Ao Ren; Olivia Chen; Ning Liu 007; Caiwen Ding; Xuehai Qian; Jie Han 001; Wenhui Luo; Nobuyuki Yoshikawa; Yanzhi Wang (CoRR, 2019)

Serial concatenated convolutional code encoder in quantum-dot cellular automata. - Yongqiang Zhang 006; Guangjun Xie; Jie Han 001 (Nano Commun. Networks, 2019)

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation. - Honglan Jiang; Leibo Liu; Fabrizio Lombardi; Jie Han 001 (IEEE Trans. Computers, 2019)

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. - Liang Wang 020; Ping Lv; Leibo Liu; Jie Han 001; Ho-fung Leung; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei; Terrence S. T. Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. - Honglan Jiang; Leibo Liu; Pieter P. Jonker; Duncan G. Elliott; Fabrizio Lombardi; Jie Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery. - Honglan Jiang; Cong Liu 015; Fabrizio Lombardi; Jie Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing. - Yidong Liu; Leibo Liu; Fabrizio Lombardi; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology. - Liang Wang 020; Leibo Liu; Xiaohang Wang 001; Jie Han 001; Chenchen Deng; Shaojun Wei (DAC, 2020)

Dynamic Stochastic Computing for Digital Signal Processing Applications. - Siting Liu 001; Jie Han 001 (DATE, 2020)

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis. - Morgan Ledwon; Bruce F. Cockburn; Jie Han 001 (IEEE Access, 2020)

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. - Leibo Liu; Jianfeng Zhu 001; Zhaoshi Li; Yanan Lu; Yangdong Deng; Jie Han 001; Shouyi Yin; Shaojun Wei (ACM Comput. Surv., 2020)

Design, evaluation and application of approximate-truncated Booth multipliers. - Yuying Zhu 003; Weiqiang Liu 001; Peipei Yin; Tian Cao 005; Jie Han 001; Fabrizio Lombardi (IET Circuits Devices Syst., 2020)

A robust wire crossing design for thermostability and fault tolerance in quantum-dot cellular automata. - Yongqiang Zhang 006; Guangjun Xie; Jie Han 001 (Microprocess. Microsystems, 2020)

Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications. - Honglan Jiang; Francisco Javier Hernandez Santiago; Hai Mo; Leibo Liu; Jie Han 001 (Proc. IEEE, 2020)

A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis. - Sanbao Su; Chen Zou 001; Weijiang Kong; Jie Han 001; Weikang Qian (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Aggressive Fine-Grained Power Gating of NoC Buffers. - Yibo Wu; Leibo Liu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Chenchen Deng; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Profile-Based Output Error Compensation for Approximate Arithmetic Circuits. - Ke Chen 018; Weiqiang Liu 001; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Circuits Syst., 2020)

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. - Liang Wang 020; Leibo Liu; Jie Han 001; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2020)

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. - Mohammad Saeed Ansari; Vojtech Mrazek; Bruce F. Cockburn; Lukás Sekanina; Zdenek Vasícek; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks. - Zijing Niu; Honglan Jiang; Mohammad Saeed Ansari; Bruce F. Cockburn; Leibo Liu; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2021)

Solving Traveling Salesman Problems Using Ising Models with Simulated Bifurcation. - Tingting Zhang; Qichao Tao; Jie Han 001 (ISOCC, 2021)

A Review of Deterministic Approaches to Stochastic Computing. - Zhendong Lin; Guangjun Xie; Shaowei Wang; Jie Han 001; Yongqiang Zhang 006 (NANOARCH, 2021)

Absolute Subtraction and Division Circuits Using Uncorrelated Random Bitstreams in Stochastic Computing. - Yuancheng Zhou; Guangjun Xie; Jie Han 001; Yongqiang Zhang 006 (NANOARCH, 2021)

Design and Implementation of a Highly Accurate Stochastic Spiking Neural Network. - Chengcheng Tang; Jie Han 001 (SiPS, 2021)

Dropout Prediction Variation Estimation Using Neuron Activation Strength. - Haichao Yu; Zhe Chen; Dong Lin; Gil I. Shamir; Jie Han 001 (CoRR, 2021)

Fast and low-power leading-one detectors for energy-efficient logarithmic computing. - Mohammad Saeed Ansari; Shyama Gandhi; Bruce F. Cockburn; Jie Han 001 (IET Comput. Digit. Tech., 2021)

An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing. - Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (IEEE Trans. Computers, 2021)

A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates. - Honglan Jiang; Shaahin Angizi; Deliang Fan; Jie Han 001; Leibo Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization. - Tian Yuan; Weiqiang Liu 001; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Accelerating Stochastic Computing Using Deterministic Halton Sequences. - Zhendong Lin; Guangjun Xie; Wenbing Xu; Jie Han 001; Yongqiang Zhang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design. - Shanshan Liu 001; Pedro Reviriego; Jing Guo 004; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2021)

A Survey of Stochastic Computing Neural Networks for Machine Learning Applications. - Yidong Liu; Siting Liu 001; Yanzhi Wang; Fabrizio Lombardi; Jie Han 001 (IEEE Trans. Neural Networks Learn. Syst., 2021)

Approximate Computing for Efficient Neural Network Computation: A Survey. - Hao Zhang 041; Mohammadreza Asadikouhanjani; Jie Han 001; Deivalakshmi Subbian; Seok-Bum Ko (Approximate Computing, 2022)

Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications. - Tingting Zhang; Honglan Jiang; Weiqiang Liu 001; Fabrizio Lombardi; Leibo Liu; Seok-Bum Ko; Jie Han 001 (Approximate Computing, 2022)

Solving traveling salesman problems via a parallel fully connected ising machine. - Qichao Tao; Jie Han 001 (DAC, 2022)

Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated Bifurcation. - Tingting Zhang; Jie Han 001 (DATE, 2022)

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Jianfeng Zhu 001; Honglan Jiang; Shouyi Yin; Shaojun Wei; Leibo Liu (HPCA, 2022)

Adversarial Fine-tune with Dynamically Regulated Adversary. - Pengyue Hou; Ming Zhou; Jie Han 001; Petr Musílek; Xingyu Li (IJCNN, 2022)

A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization. - Tingting Zhang; Qichao Tao; Bailiang Liu; Jie Han 001 (ISCAS, 2022)

A Brief Review of Logarithmic Multiplier Designs. - Tingting Zhang; Zijing Niu; Jie Han 001 (LATS, 2022)

Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing. - Shaowei Wang; Guangjun Xie; Jie Han 001; Yongqiang Zhang 006 (Int. J. Circuit Theory Appl., 2022)

A stochastic computing architecture for local contrast and mean image thresholding algorithm. - Wenbing Xu; Guangjun Xie; Shaowei Wang; Zhendong Lin; Jie Han 001; Yongqiang Zhang 006 (Int. J. Circuit Theory Appl., 2022)

A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators. - Mario Barbareschi; Salvatore Barone; Alberto Bosio; Jie Han 001; Marcello Traiola (ACM J. Emerg. Technol. Comput. Syst., 2022)

Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations. - Francisco Javier Hernandez Santiago; Honglan Jiang; Hussam Amrouch; Andreas Gerstlauer; Leibo Liu; Jie Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation. - Yong Wu; Honglan Jiang; Zining Ma; Pengfei Gou; Yong Lu; Jie Han 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Low-Power Approximate Logarithmic Squaring Circuit Design for DSP Applications. - Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers. - Haroon Waris; Chenghua Wang; Weiqiang Liu 001; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2022)

Improving Adversarial Robustness with Self-Paced Hard-Class Pair Reweighting. - Pengyue Hou; Jie Han 001; Xingyu Li (AAAI, 2023)

Hardware Efficient Weight-Binarized Spiking Neural Networks. - Chengcheng Tang; Jie Han 001 (DATE, 2023)

Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications. - Yongqiang Zhang 006; Lingyun Xie; Jie Han 001; Xin Cheng 001; Guangjun Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing. - Xuemei Fan; Tingting Zhang; Hao Liu 013; Shengli Lu; Jie Han 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Guest Editorial Unconventional Computing Techniques for Emerging Technology Applications. - Paul P. Sotiriadis; Jie Han 001; M. Hassan Najafi; Josep Lluís Rosselló Sanz (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators. - Tong Li; Honglan Jiang; Hai Mo; Jie Han 001; Leibo Liu; Zhi-Gang Mao (J. Comput. Sci. Technol., 2023)

Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. - Alberto Bosio; Mario Barbareschi; Alessandro Savino; Jie Han 001; Jürgen Teich (IEEE Des. Test, 2023)

An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths. - Yongqiang Zhang 006; Siting Liu 001; Jie Han 001; Zhendong Lin; Shaowei Wang; Xin Cheng 001; Guangjun Xie (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Approximate Parallel Annealing Ising Machine for Solving Traveling Salesman Problems. - Qichao Tao; Tingting Zhang; Jie Han 001 (IEEE Embed. Syst. Lett., 2023)

QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference. - Xinkuang Geng; Siting Liu 001; Leibo Liu; Jie Han 001; Honglan Jiang (DAC, 2024)

Efficient Approximate Decomposition Solver using Ising Model. - Weihua Xiao; Tingting Zhang; Xingyue Qian; Jie Han 001; Weikang Qian (DAC, 2024)

A High-Performance Stochastic Simulated Bifurcation Ising Machine. - Tingting Zhang; Hongqiao Zhang; Zhengkun Yu; Siting Liu 001; Jie Han 001 (DAC, 2024)

A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System. - Wenhui Zhang; Xinkuang Geng; Qin Wang 009; Jie Han 001; Honglan Jiang (ACM Great Lakes Symposium on VLSI, 2024)

An Architectural Error Metric for CNN-Oriented Approximate Multipliers. - Ao Liu; Jie Han 001; Qin Wang 009; Zhigang Mao; Honglan Jiang (CoRR, 2024)

A Low-Cost and Fault-Tolerant Stochastic Architecture for the Bernsen Algorithm Using Bitstream Correlation. - Shaowei Wang; Guangjun Xie; Wenbing Xu; Yongqiang Zhang 006; Jie Han 001 (J. Circuits Syst. Comput., 2024)

A Design Framework for Hardware-Efficient Logarithmic Floating-Point Multipliers. - Tingting Zhang; Zijing Niu; Jie Han 001 (IEEE Trans. Emerg. Top. Comput., 2024)

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications. - Zijing Niu; Tingting Zhang; Honglan Jiang; Bruce F. Cockburn; Leibo Liu; Jie Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits. - Ying Wu; Chuangtao Chen 001; Weihua Xiao; Xuan Wang; Chenyi Wen; Jie Han 001; Xunzhao Yin; Weikang Qian; Cheng Zhuo (ACM Trans. Design Autom. Electr. Syst., 2024)

Stochastic Mean Circuits Based on Inner-Product Units Using Correlated Bitstreams. - Yongqiang Zhang 006; Xiaoyue Chen; Jie Han 001; Guangjun Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Learning the Error Features of Approximate Multipliers for Neural Network Applications. - Hai Mo; Yong Wu; Honglan Jiang; Zining Ma; Fabrizio Lombardi; Jie Han 001; Leibo Liu (IEEE Trans. Computers, 2024)

Design of a Stochastic Computing Architecture for the Phansalkar Algorithm. - Yongqiang Zhang 006; Jiao Qin; Jie Han 001; Guangjun Xie (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Lookup Table Refactoring: Towards Efficient Logarithmic Number System Addition for Large Language Models. - Xinkuang Geng; Siting Liu 001; Hui Wang 023; Jie Han 001; Honglan Jiang (DATE, 2025)

A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks. - Xiaolu Hu; Xinkuang Geng; Zhigang Mao; Jie Han 001; Honglan Jiang (DATE, 2025)

An SRAM-based Stochastic Number Generator for Stochastic Computing. - Heng Shi; Zhengkun Yu; Tingting Zhang; Jie Han 001; Yumeng Yang; Siting Liu 001 (ISCAS, 2025)