BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. - Jie-Hong R. Jiang; Jing-Yang Jou; Juinn-Dar Huang; Jung-Shian Wei (ASP-DAC, 1997)

Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. - Jie-Hong Roland Jiang; Jing-Yang Jou; Juinn-Dar Huang (DAC, 1998)

Optimum loading dispersion for high-speed tree-type decision circuitry. - Jie-Hong Roland Jiang; Iris Hui-Ru Jiang (ICCAD, 1999)

Unified functional decomposition via encoding for FPGA technology mapping. - Jie-Hong Roland Jiang; Jing-Yang Jou; Juinn-Dar Huang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Optimization of Multi-Valued Multi-Level Networks. - Robert K. Brayton; M. Gao; Jie-Hong Roland Jiang; Yunjian Jiang; Yinghua Li; Alan Mishchenko; Subarnarekha Sinha; Tiziano Villa (ISMVL, 2002)

Reducing Multi-Valued Algebraic Operations to Binary. - Jie-Hong Roland Jiang; Alan Mishchenko; Robert K. Brayton (IWLS, 2002)

On the verification of sequential equivalence. - Jie-Hong Roland Jiang; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Functional Dependency for Verification Reduction. - Jie-Hong Roland Jiang; Robert K. Brayton (CAV, 2004)

On breakable cyclic definitions. - Jie-Hong Roland Jiang; Alan Mishchenko; Robert K. Brayton (ICCAD, 2004)

Efficient Solution of Language Equations Using Partitioned Representations. - Alan Mishchenko; Robert K. Brayton; Jie-Hong Roland Jiang; Tiziano Villa; Nina Yevtushenko 001 (DATE, 2005)

On Some Transformation Invariants Under Retiming and Resynthesis. - Jie-Hong Roland Jiang (TACAS, 2005)

Retiming and Resynthesis: A Complexity Perspective. - Jie-Hong Roland Jiang; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Inductive equivalence checking under retiming and resynthesis. - Jie-Hong Roland Jiang; Wei-Lun Hung (ICCAD, 2007)

Scalable exploration of functional dependency by interpolation and incremental SAT solving. - Chih-Chun Lee; Jie-Hong Roland Jiang; Chung-Yang Huang; Alan Mishchenko (ICCAD, 2007)

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. - Chin-Hsiung Hsu; Szu-Jui Chou; Jie-Hong Roland Jiang; Yao-Wen Chang (PATMOS, 2007)

Quantum Mechanical Search and Harmonic Perturbation. - Jie-Hong R. Jiang; Dah-Wei Chiou; Cheng-En Wu (Quantum Inf. Process., 2007)

Bi-decomposing large Boolean functions via interpolation and satisfiability solving. - Ruei-Rung Lee; Jie-Hong Roland Jiang; Wei-Lun Hung (DAC, 2008)

To SAT or not to SAT: Ashenhurst decomposition in a large scale. - Hsuan-Po Lin; Jie-Hong Roland Jiang; Ruei-Rung Lee (ICCAD, 2008)

A dynamic accuracy-refinement approach to timing-driven technology mapping. - Sz-Cheng Huang; Jie-Hong Roland Jiang (ICCD, 2008)

Quantifier Elimination via Functional Composition. - Jie-Hong R. Jiang (CAV, 2009)

Interpolating functions from large Boolean relations. - Jie-Hong Roland Jiang; Hsuan-Po Lin; Wei-Lun Hung (ICCAD, 2009)

Hardware Equivalence and Property Verification. - Jie-Hong Roland Jiang; Tiziano Villa; Yves Crama; Peter L. Hammer (Boolean Models and Methods, 2010)

BooM: a decision procedure for boolean matching with abstraction and dynamic learning. - Chih-Fan Lai; Jie-Hong R. Jiang; Kuo-Hua Wang (DAC, 2010)

Boolean matching of function vectors with strengthened learning. - Chih-Fan Lai; Jie-Hong R. Jiang; Kuo-Hua Wang (ICCAD, 2010)

A robust functional ECO engine by SAT proof minimization and interpolation techniques. - Bo-Han Wu; Chun-Ju Yang; Chung-Yang Huang; Jie-Hong Roland Jiang (ICCAD, 2010)

To SAT or Not to SAT: Scalable Exploration of Functional Dependency. - Jie-Hong Roland Jiang; Chih-Chun Lee; Alan Mishchenko; Chung-Yang Huang (IEEE Trans. Computers, 2010)

Resolution Proofs and Skolem Functions in QBF Evaluation and Applications. - Valeriy Balabanov; Jie-Hong R. Jiang (CAV, 2011)

Towards completely automatic decoder synthesis. - Hsiou-Yuan Liu; Yen-Cheng Chou; Chen-Hsuan Lin 001; Jie-Hong R. Jiang (ICCAD, 2011)

Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. - Chia-Wei Chang; Hong-Zu Chou; Kai-Hui Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu; Chiu-Han Hsiao; Sy-Yen Kuo (ISQED, 2011)

Scalable don't-care-based logic optimization and resynthesis. - Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Stephen Jang (ACM Trans. Reconfigurable Technol. Syst., 2011)

Clock rescheduling for timing engineering change orders. - Kuan-Hsien Ho; Xin-Wei Shih; Jie-Hong R. Jiang (ASP-DAC, 2012)

When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way. - Cheng-Shen Han; Jie-Hong Roland Jiang (CAV, 2012)

Compiling program control flows into biochemical reactions. - De-An Huang; Jie-Hong R. Jiang; Ruei-Yang Huang; Chi-Yun Cheng (ICCAD, 2012)

Improving design verifiability by early RTL coverability analysis. - Kai-Hui Chang; Chia-Wei Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu (MEMOCODE, 2012)

Reducing test point overhead with don't-cares. - Kai-Hui Chang; Chia-Wei Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu (MWSCAS, 2012)

Henkin Quantifiers and Boolean Formulae. - Valeriy Balabanov; Hui-Ju Katherine Chiang; Jie-Hong Roland Jiang (SAT, 2012)

Unified QBF certification and its applications. - Valeriy Balabanov; Jie-Hong R. Jiang (Formal Methods Syst. Des., 2012)

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. - Kuan-Hsien Ho; Jie-Hong Roland Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Automatic Decoder Synthesis: Methods and Case Studies. - Hsiou-Yuan Liu; Yen-Cheng Chou; Chen-Hsuan Lin 001; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models. - Hui-Ju Katherine Chiang; François Fages; Jie-Hong R. Jiang; Sylvain Soliman (CMSB, 2013)

Synthesis of feedback decoders for initialized encoders. - Kuan-Hua Tu; Jie-Hong R. Jiang (DAC, 2013)

Synthesizing multiple boolean functions using interpolation on a single proof. - Georg Hofferek; Ashutosh Gupta; Bettina Könighofer; Jie-Hong Roland Jiang; Roderick Bloem (FMCAD, 2013)

Automatic test pattern generation for delay defects using timed characteristic functions. - Shin-Yann Ho; Shuo-Ren Lin; Ko-Lung Yuan; Chien-Yen Kuo; Kuan-Yu Liao; Jie-Hong R. Jiang; Chien-Mo James Li (ICCAD, 2013)

Encoding multi-valued functions for symmetry. - Ko-Lung Yuan; Chien-Yen Kuo; Jie-Hong R. Jiang; Meng-Yen Li (ICCAD, 2013)

Functional Timing Analysis Made Fast and General. - Yi-Ting Chung; Jie-Hong Roland Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Software Workarounds for Hardware Errors: Instruction Patch Synthesis. - Tsung-Po Liu; Shuo-Ren Lin; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Building reconfigurable circuitry in a biochemical world. - Hui-Ju Katherine Chiang; Jie-Hong R. Jiang; François Fages (BioCAS, 2014)

Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. - Chi-Chuan Chuang; Yi-Hsiang Lai; Jie-Hong R. Jiang (DAC, 2014)

Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. - Chi-Yuan Liu; Hui-Ju Katherine Chiang; Yao-Wen Chang; Jie-Hong R. Jiang (DAC, 2014)

QBF Resolution Systems and Their Proof Complexities. - Valeriy Balabanov; Magdalena Widl; Jie-Hong R. Jiang (SAT, 2014)

Henkin quantifiers and Boolean formulae: A certification perspective of DQBF. - Valeriy Balabanov; Hui-Ju Katherine Chiang; Jie-Hong R. Jiang (Theor. Comput. Sci., 2014)

Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs. - Valeriy Balabanov; Jie-Hong Roland Jiang; Mikolas Janota; Magdalena Widl (AAAI, 2015)

Scalable sequence-constrained retention register minimization in power gating design. - Ting-Wei Chiang; Kai-Hui Chang; Yen-Ting Liu; Jie-Hong R. Jiang (DAC, 2015)

Reconfigurable neuromorphic computation in biochemical systems. - Hui-Ju Katherine Chiang; Jie-Hong R. Jiang; François Fages (EMBC, 2015)

Property-Directed Synthesis of Reactive Systems from Safety Specifications. - Ting-Wei Chiang; Jie-Hong R. Jiang (ICCAD, 2015)

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. - Bo-Yuan Huang 001; Yi-Hsiang Lai; Jie-Hong Roland Jiang (ICCAD, 2015)

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. - Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang (ICCAD, 2015)

SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. - Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong Roland Jiang (ICCAD, 2015)

QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving. - Kuan-Hua Tu; Tzu-Chien Hsu; Jie-Hong R. Jiang (SAT, 2015)

Deriving Compositionally Deadlock-Free Components over Synchronous Automata Compositions. - Nina Yevtushenko 001; Khaled El-Fakih; Tiziano Villa; Jie-Hong R. Jiang (Comput. J., 2015)

Hybrid Simulations of Heterogeneous Biochemical Models in SBML. - Hui-Ju Katherine Chiang; François Fages; Jie-Hong Roland Jiang; Sylvain Soliman (ACM Trans. Model. Comput. Simul., 2015)

Clauses Versus Gates in CEGAR-Based 2QBF Solving. - Valeriy Balabanov; Jie-Hong Roland Jiang; Alan Mishchenko; Christoph Scholl 001 (AAAI Workshop: Beyond NP, 2016)

String Analysis via Automata Manipulation with Logic Circuit Representation. - Hung-En Wang; Tzung-Lin Tsai; Chun-Han Lin; Fang Yu 001; Jie-Hong R. Jiang (CAV (1), 2016)

Design partitioning for large-scale equivalence checking and functional correction. - Grace Wu; Yi-Tin Sun; Jie-Hong R. Jiang (DAC, 2016)

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. - Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang (ICCAD, 2016)

2QBF: Challenges and Solutions. - Valeriy Balabanov; Jie-Hong Roland Jiang; Christoph Scholl 001; Alan Mishchenko; Robert K. Brayton (SAT, 2016)

Flexibility and Optimization of QBF Skolem-Herbrand Certificates. - Valeriy Balabanov; Shuo-Ren Lin; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. - Hui-Ju Katherine Chiang; Chi-Yuan Liu; Jie-Hong R. Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. - Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines. - Chun-Hong Shih; Jie-Hong R. Jiang (ASYNC, 2017)

Recombinase-based genetic circuit optimization. - Chun-Ning Lai; Jie-Hong R. Jiang; François Fages (BioCAS, 2017)

Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation. - Chun-Ning Lai; Jie-Hong R. Jiang (DAC, 2017)

Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits. - Cheng-Yu Shih; Chun-Hong Shih; Jie-Hong R. Jiang (DAC, 2017)

Sequential engineering change order under retiming and resynthesis. - Nian-Ze Lee; Victor N. Kravets; Jie-Hong R. Jiang (ICCAD, 2017)

Solving Stochastic Boolean Satisfiability under Random-Exist Quantification. - Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang (IJCAI, 2017)

Homing Sequence Derivation with Quantified Boolean Satisfiability. - Hung-En Wang; Kuan-Hua Tu; Jie-Hong R. Jiang; Natalia Kushik (ICTSS, 2017)

A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning. - Hsiao-Lei Chien; Mei-Yen Chiu; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Efficient computation of ECO patch functions. - Ai Quoc Dao; Nian-Ze Lee; Li-Cheng Chen; Mark Po-Hung Lin; Jie-Hong R. Jiang; Alan Mishchenko; Robert K. Brayton (DAC, 2018)

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. - Run-Yi Wang; Chia-Cheng Pai; Jun-Jie Wang; Hsiang-Ting Wen; Yu-Cheng Pai; Yao-Wen Chang; James Chien-Mo Li; Jie-Hong Roland Jiang (DAC, 2018)

Cost-aware patch generation for multi-target function rectification of engineering change orders. - He-Teng Zhang; Jie-Hong R. Jiang (DAC, 2018)

Canonicalization of threshold logic representation and its applications. - Siang-Yun Lee; Nian-Ze Lee; Jie-Hong R. Jiang (ICCAD, 2018)

Static detection of API call vulnerabilities in iOS executables. - Chun-Han Lin; Fang Yu 001; Jie-Hong Roland Jiang; Tevfik Bultan (ICSE (Companion Volume), 2018)

Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection. - Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang (IJCAI, 2018)

A symbolic model checking approach to the analysis of string and length constraints. - Hung-En Wang; Shih-Yu Chen; Fang Yu 001; Jie-Hong R. Jiang (ASE, 2018)

Towards Formal Evaluation and Verification of Probabilistic Design. - Nian-Ze Lee; Jie-Hong R. Jiang (IEEE Trans. Computers, 2018)

A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving. - Christoph Scholl 001; Jie-Hong Roland Jiang; Ralf Wimmer 001; Aile Ge-Ernst (AAAI, 2019)

An approximation algorithm to the optimal switch control of reconfigurable battery packs. - Shih-Yu Chen; Jie-Hong R. Jiang; Shou-Hung Welkin Ling; Shih-Hao Liang; Mao-Cheng Huang (ASP-DAC, 2019)

Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. - Yi-Fan Evan Chang; Ruei-Yang Huang; Jie-Hong R. Jiang (ASYNC, 2019)

Biochemical Threshold Function Implementation with Zero-Order Ultrasensitivity. - Wei-Chih Huang; Jie-Hong Roland Jiang; François Fages; Franck Molina (BioCAS, 2019)

A Cube Distribution Approach to QBF Solving and Certificate Minimization. - Li-Cheng Chen; Jie-Hong R. Jiang (CP, 2019)

Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis. - Hao Chen; Shao-Chun Hung; Jie-Hong R. Jiang (DAC, 2019)

Comprehensive Search for ECO Rectification Using Symbolic Sampling. - Victor N. Kravets; Nian-Ze Lee; Jie-Hong R. Jiang (DAC, 2019)

Time-Frame Folding: Back to the Sequentiality. - Po-Chun Chien; Jie-Hong R. Jiang (ICCAD, 2019)

Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. - Siang-Yun Lee; Nian-Ze Lee; Jie-Hong R. Jiang (ICCAD, 2019)

Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits. - Zi-Jun Lin; Wei-Chih Huang; Jie-Hong Roland Jiang (ISMVL, 2019)

Circuit Learning for Logic Regression on High Dimensional Boolean Space. - Pei-Wei Chen; Yu-Ching Huang; Cheng-Lin Lee; Jie-Hong Roland Jiang (DAC, 2020)

Time Multiplexing via Circuit Folding. - Po-Chun Chien; Jie-Hong R. Jiang (DAC, 2020)

SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. - He-Teng Zhang; Jie-Hong R. Jiang (DAC, 2020)

Engineering Change Order for Combinational and Sequential Design Rectification. - Jie-Hong R. Jiang; Victor N. Kravets; Nian-Ze Lee (DATE, 2020)

Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. - Victor N. Kravets; Jie-Hong R. Jiang; Heinz Riener (DATE, 2020)

Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning. - Yu-Chou Lin; Jie-Hong R. Jiang (ICCAD, 2020)

Symbolic Uniform Sampling with XOR Circuits. - Yen-Ting Lin; Jie-Hong R. Jiang; Victor N. Kravets (ICCAD, 2020)

Symbolic Gas Vulnerability Detection and Attack Synthesis. - Min Hao Peng; Fang Yu 001; Jie-Hong Roland Jiang (PACIS, 2020)

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation to a New Level. - Yuan-Hung Tsai; Jie-Hong R. Jiang; Chiao-Shan Jhang (CoRR, 2020)

A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving. - Pei-Wei Chen; Yu-Ching Huang; Jie-Hong R. Jiang (AAAI, 2021)

Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. - Nian-Ze Lee; Jie-Hong R. Jiang (AAAI, 2021)

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation. - Yuan-Hung Tsai; Jie-Hong R. Jiang; Chiao-Shan Jhang (DAC, 2021)

Deep Integration of Circuit Simulator and SAT Solver. - He-Teng Zhang; Jie-Hong R. Jiang; Luca G. Amarù; Alan Mishchenko; Robert K. Brayton (DAC, 2021)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Compatible Equivalence Checking of X-Valued Circuits. - Yu-Neng Wang; Yun-Rong Luo; Po-Chun Chien; Ping-Lun Wang; Hao-Ren Wang; Wan-Hsuan Lin; Jie-Hong Roland Jiang; Chung-Yang (Ric) Huang (ICCAD, 2021)

A Circuit-Based SAT Solver for Logic Synthesis. - He-Teng Zhang; Jie-Hong R. Jiang; Alan Mishchenko (ICCAD, 2021)

Constraint Solving for Synthesis and Verification of Threshold Logic Circuits. - Nian-Ze Lee; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

SAT-Based On-Track Bus Routing. - He-Teng Zhang; Masahiro Fujita; Chung-Kuan Cheng; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Reconfigurable Biochemical Circuit Synthesis from Biomachine Specification. - Chang-Jun Wang; Jie-Hong R. Jiang (BioCAS, 2022)

Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification. - Chun-Yu Wei; Yuan-Hung Tsai; Chiao-Shan Jhang; Jie-Hong R. Jiang (DAC, 2022)

Language Equation Solving via Boolean Automata Manipulation. - Wan-Hsuan Lin; Chia-Hsuan Su; Jie-Hong R. Jiang (ICCAD, 2022)

Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability. - Cheng-Han Hsieh; Jie-Hong R. Jiang (IJCAI, 2022)

Partial Equivalence Checking of Quantum Circuits. - Tian-Fu Chen; Jie-Hong R. Jiang; Min-Hsiu Hsieh (QCE, 2022)

Quantifier Elimination in Stochastic Boolean Satisfiability. - Hao-Ren Wang; Kuan-Hua Tu; Jie-Hong Roland Jiang; Christoph Scholl 001 (SAT, 2022)

Design and Automation for Quantum Computation and Quantum Technologies. - Jie-Hong R. Jiang; Giovanni De Micheli; Kaitlin N. Smith; Mathias Soeken (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective. - Giovanni De Micheli; Jie-Hong R. Jiang; Robert Rand 001; Kaitlin N. Smith; Mathias Soeken (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Homing Sequence Derivation With Quantified Boolean Satisfiability. - Kuan-Hua Tu; Hung-En Wang; Jie-Hong R. Jiang; Natalia Kushik; Nina Yevtushenko 001 (IEEE Trans. Computers, 2022)

Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation. - Chia-Chih Chi; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Lifting (D)QBF Preprocessing and Solving Techniques to (D)SSAT. - Che Cheng; Jie-Hong R. Jiang (AAAI, 2023)

SharpSSAT: A Witness-Generating Stochastic Boolean Satisfiability Solver. - Yu-Wei Fan; Jie-Hong R. Jiang (AAAI, 2023)

Second-Order Quantified Boolean Logic. - Jie-Hong R. Jiang (AAAI, 2023)

Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration. - Chun-Yu Wei; Jie-Hong R. Jiang (DAC, 2023)

WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits. - Kuo-Wei Ho; Shao-Ting Chung; Tian-Fu Chen; Yu-Wei Fan; Che Cheng; Cheng-Han Liu; Jie-Hong R. Jiang (ICCAD, 2023)

VanQiRA: A Vanishing-State-Based Framework for Quantum Circuit Runtime Assertion. - Tian-Fu Chen; Chun-Yu Wei; Jie-Hong R. Jiang (QCE, 2023)

Quantized Neural Network Synthesis for Direct Logic Circuit Implementation. - Yu-Shan Huang; Jie-Hong R. Jiang; Alan Mishchenko (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Resolution Proof System for Dependency Stochastic Boolean Satisfiability. - Yun-Rong Luo; Che Cheng; Jie-Hong R. Jiang (J. Autom. Reason., 2023)

Circuit Learning: From Decision Trees to Decision Graphs. - Yu-Shan Huang; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Unifying Decision and Function Queries in Stochastic Boolean Satisfiability. - Yu-Wei Fan; Jie-Hong R. Jiang (AAAI, 2024)

Boolean Matching Reversible Circuits: Algorithm and Complexity. - Tian-Fu Chen; Jie-Hong Roland Jiang (DAC, 2024)

2-DQBF Solving and Certification via Property-Directed Reachability Analysis. - Long-Hin Fung; Che Cheng; Yu-Wei Fan; Tony Tan; Jie-Hong Roland Jiang (FMCAD, 2024)

Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization. - Tian-Fu Chen; Yu-Fang Chen 001; Jie-Hong Roland Jiang; Sára Jobranová; Ondrej Lengál (ICCAD, 2024)

Knowledge Compilation for Incremental and Checkable Stochastic Boolean Satisfiability. - Che Cheng; Yun-Rong Luo; Jie-Hong R. Jiang (IJCAI, 2024)

Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems. - Wei-Hsiang Tseng; Yao-Wen Chang; Jie-Hong Roland Jiang (ISPD, 2024)

A Holistic Approach to Rotation Synthesis for Fault- Tolerant Quantum Computation. - Tian-Fu Chen; Cheng-Han Liu; Jie-Hong R. Jiang (QCE, 2024)

Enhanced Quantum Circuit Cutting Framework for Sampling Overhead Reduction. - Po-Hung Chen; Dah-Wei Chiou; Jie-Hong Roland Jiang (CoRR, 2024)

Solving Higher-Order Quantified Boolean Satisfiability via Higher-Order Model Checking. - Hiroshi Unno 001; Takeshi Tsukada; Jie-Hong Roland Jiang (AAAI, 2025)

Fine-Grained Complexity Analysis of Dependency Quantified Boolean Formulas. - Che Cheng; Long-Hin Fung; Jie-Hong Roland Jiang; Friedrich Slivovsky; Tony Tan (SAT, 2025)

SliQSim: A Quantum Circuit Simulator and Solver for Probability and Statistics Queries. - Tian-Fu Chen; Jie-Hong R. Jiang (TACAS (3), 2025)