Simulating Open-Via Defects. - Stefan Spinner; Jie Jiang 018; Ilia Polian; Piet Engelke; Bernd Becker 001 (ATS, 2007)

Efficient SAT-Based Search for Longest Sensitisable Paths. - Matthias Sauer 002; Jie Jiang 018; Alejandro Czutro; Ilia Polian; Bernd Becker 001 (Asian Test Symposium, 2011)

On the optimality of K longest path generation algorithm under memory constraints. - Jie Jiang 018; Matthias Sauer 002; Alexander Czutro; Bernd Becker 001; Ilia Polian (DATE, 2012)

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. - Jie Jiang 018; Marina Aparicio; Mariane Comte; Florence Azaïs; Michel Renovell; Ilia Polian (Asian Test Symposium, 2013)

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. - Marina Aparicio; Mariane Comte; Florence Azaïs; Michel Renovell; Jie Jiang 018; Ilia Polian; Bernd Becker 001 (LATW, 2013)

Detection conditions for errors in self-adaptive better-than-worst-case designs. - Ilia Polian; Jie Jiang 018; Adit D. Singh (ETS, 2014)

On Optimal Power-Aware Path Sensitization. - Matthias Sauer 002; Jie Jiang 018; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker 001; Ilia Polian (ATS, 2016)

Delay Testing in Nanoscale Technology under Process Variations - Jie Jiang 018 (2016)