Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories. - Liyi Xiao; Jiaqiang Li; Jie Li 030; Jing Guo 004 (ISQED, 2015)

A method to estimate cross-section of circuits at RTL levels. - Liyi Xiao; Anlong Li; Xuebing Cao; Hongchen Li; Rongsheng Zhang; Jie Li 030; Tianqi Wang (ASICON, 2017)

A fast and accurate fault injection platform for SRAM-based FPGAs. - Rongsheng Zhang; Liyi Xiao; Jie Li 030 (ASICON, 2017)

Low redundancy matrix-based codes for adjacent error correction with parity sharing. - Shanshan Liu 001; Liyi Xiao; Jie Li 030; Yihan Zhou; Zhigang Mao (ISQED, 2017)

Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm. - Xuebing Cao; Liyi Xiao; Linzhe Li; Jie Li 030; Jiaqiang Li; Jinxiang Wang 001 (IOLTS, 2018)

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs. - Rongsheng Zhang; Liyi Xiao; Jie Li 030; Xuebing Cao; Chunhua Qi; Jiaqiang Li; Mingjiang Wang (Microelectron. Reliab., 2018)

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. - Jiaqiang Li; Pedro Reviriego; Liyi Xiao; Costas Argyrides; Jie Li 030 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology. - Hongchen Li; Liyi Xiao; Jie Li 030; He Liu (ASICON, 2019)

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. - Linzhe Li; Liyi Xiao; Jie Li 030; He Liu; Zhigang Mao (ASICON, 2019)

A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network. - Jie Li 030; Liyi Xiao; Hongchen Li; Lulu Liao; Chenxu Wang (ASICON, 2019)

Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. - Xuebing Cao; Liyi Xiao; Linzhe Li; Jie Li 030; Tianqi Wang (ICICDT, 2019)

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs). - Xuebing Cao; Liyi Xiao; Jie Li 030; Rongsheng Zhang; Shanshan Liu 001; Jinxiang Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Scheme for periodical concurrent fault detection in parallel CRC circuits. - Jie Li 030; Shanshan Liu 001; Pedro Reviriego; Liyi Xiao; Fabrizio Lombardi (IET Comput. Digit. Tech., 2020)

An Adjustable and Fast Error Repair Scrubbing Method Based on Xilinx Essential Bits Technology for SRAM-Based FPGA. - Rongsheng Zhang; Liyi Xiao; Jie Li 030; Xuebing Cao; Linzhe Li (IEEE Trans. Reliab., 2020)

Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH). - Jie Li 030; Pedro Reviriego; Shanshan Liu 001; Liyi Xiao; Fabrizio Lombardi (Integr., 2021)

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets. - Hongchen Li; Liyi Xiao; Chunhua Qi; Jie Li 030 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors. - Jie Li 030; Liyi Xiao; Linzhe Li; Hongchen Li; He Liu; Chenxu Wang (IEEE Access, 2022)

A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs. - Jie Li 030; Liyi Xiao; Linzhe Li; Hongchen Li; He Liu; Chenxu Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

SET-detection low complexity burst error correction codes for SRAM protection. - He Liu; Jiaqiang Li; Liyi Xiao; Tianqi Wang; Jie Li 030 (Integr., 2024)

Error Correction Codes for Double Burst Errors Correction in Memories. - He Liu; Liyi Xiao; Tianqi Wang; Jiaqiang Li; Jie Li 030 (IEEE Access, 2025)