A high speed pipeline ADC with 78-dB SFDR in 0.18 um BiCMOS. - Jie Sun 020; Jianhui Wu 001 (ISIC, 2016)

A 12-bit 350 MS/s Single-Channel Pipeline ADC with 75 dB SFDR in 0.18 μm BiCMOS. - Jie Sun 020; Jianhui Wu 001 (J. Circuits Syst. Comput., 2019)

A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator. - Chenggang Yan 002; Jianhui Wu 001; Jie Sun 020; Jin Jin; Chen Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators. - Jie Sun 020; Minglei Zhang; Lei Qiu 002; Jianhui Wu 001; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique. - Chao Chen; Jie Sun 020; Chenghua Wang; Weiqiang Liu 001 (ISCAS, 2021)

A 2-Then-1 Bit/Cycle Asynchronous SAR ADC with Background Offset Calibration. - Jie Sun 020; Jun Huang; Jianhui Wu 001; Weiqiang Liu 001 (ISCAS, 2021)

Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows. - Jie Sun 020; Xin Ding 003; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Correlation-Based Background Calibration of Bit Weight in SAR ADCs Using DAS Algorithm. - Lizhen Zhang; Peng Wang; Jie Sun 020; Jianhui Wu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering. - Chenggang Yan 002; Jie Sun 020; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)