Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). - Jie Wang 022; Jason Cong (FPGA, 2015)

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. - Jiantao Qiu; Jie Wang 022; Song Yao; Kaiyuan Guo; Boxun Li; Erjin Zhou; Jincheng Yu; Tianqi Tang 001; Ningyi Xu; Sen Song; Yu Wang 002; Huazhong Yang (FPGA, 2016)

Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. - Jie Wang 022; Xinfeng Xie; Jason Cong (IPDPS, 2017)

Automatic Interior I/O Elimination in Systolic Array Architecture. - Jason Cong; Jie Wang 022 (FCCM, 2018)

PolySA: polyhedral-based systolic array auto-compilation. - Jason Cong; Jie Wang 022 (ICCAD, 2018)

Rapid Cycle-Accurate Simulator for High-Level Synthesis. - Yuze Chi; Young-kyu Choi; Jason Cong; Jie Wang 022 (FPGA, 2019)

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. - Yi-Hsiang Lai; Yuze Chi; Yuwei Hu; Jie Wang 022; Cody Hao Yu; Yuan Zhou; Jason Cong; Zhiru Zhang (FPGA, 2019)

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. - Licheng Guo; Jason Lau; Yuze Chi; Jie Wang 022; Cody Hao Yu; Zhe Chen; Zhiru Zhang; Jason Cong (DAC, 2020)

Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. - Michael Lo; Zhenman Fang; Jie Wang 022; Peipei Zhou 001; Mau-Chung Frank Chang; Jason Cong (FCCM, 2020)

End-to-End Optimization of Deep Learning Applications. - Atefeh Sohrabizadeh; Jie Wang 022; Jason Cong (FPGA, 2020)

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. - Yi-Hsiang Lai; Hongbo Rong; Size Zheng 001; Weihao Zhang; Xiuping Cui; Yunshan Jia; Jie Wang 022; Brendan Sullivan; Zhiru Zhang; Yun Liang 001; Youhui Zhang; Jason Cong; et al. (ICCAD, 2020)

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. - Young-kyu Choi; Yuze Chi; Jie Wang 022; Licheng Guo; Jason Cong (CoRR, 2020)

FLASH: Fast, Parallel, and Accurate Simulator for HLS. - Young-kyu Choi; Yuze Chi; Jie Wang 022; Jason Cong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

UNIT: Unifying Tensorized Instruction Compilation. - Jian Weng 002; Animesh Jain; Jie Wang 022; Leyuan Wang; Yida Wang 003; Tony Nowatzki (CGO, 2021)

Extending High-Level Synthesis for Task-Parallel Programs. - Yuze Chi; Licheng Guo; Jason Lau; Young-kyu Choi; Jie Wang 022; Jason Cong (FCCM, 2021)

MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. - Peipei Zhou 001; Jiayi Sheng; Cody Hao Yu; Peng Wei 004; Jie Wang 022; Di Wu 010; Jason Cong (FPGA, 2021)

AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. - Jie Wang 022; Licheng Guo; Jason Cong (FPGA, 2021)

Extending High-Level Synthesis for Task-Parallel Programs. - Yuze Chi; Licheng Guo; Young-kyu Choi; Jie Wang 022; Jason Cong (FPGA, 2021)

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. - Licheng Guo; Yuze Chi; Jie Wang 022; Jason Lau; Weikang Qiao; Ecenur Ustun; Zhiru Zhang; Jason Cong (FPGA, 2021)

Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. - Jie Wang 022; Jason Cong (CoRR, 2021)

Automatic Synthesis and Architecture Optimization of Systolic Arrays. - Jie Wang 022 (2021)

A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. - Suhail Basalama; Atefeh Sohrabizadeh; Jie Wang 022; Jason Cong (FCCM, 2022)

RapidStream: Parallel Physical Implementation of FPGA HLS Designs. - Licheng Guo; Pongstorn Maidee; Yun Zhou; Chris Lavin; Jie Wang 022; Yuze Chi; Weikang Qiao; Alireza Kaviani; Zhiru Zhang; Jason Cong (FPGA, 2022)

A Comprehensive Automated Exploration Framework for Systolic Array Designs. - Suhail Basalama; Jie Wang 022; Jason Cong (DAC, 2023)

Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUs. - Bojian Zheng; Cody Hao Yu; Jie Wang 022; Yaoyao Ding; Yizhi Liu; Yida Wang 003; Gennady Pekhimenko (MICRO, 2023)

Democratizing Domain-Specific Computing. - Yuze Chi; Weikang Qiao; Atefeh Sohrabizadeh; Jie Wang 022; Jason Cong (Commun. ACM, 2023)

RAF: Holistic Compilation for Deep Learning Model Training. - Cody Hao Yu; Haozheng Fan; Guangtai Huang; Zhen Jia 001; Yizhi Liu; Jie Wang 022; Zach Zheng; Yuan Zhou; Haichen Shen; Junru Shao; Mu Li 003; Yida Wang 003 (CoRR, 2023)

FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. - Suhail Basalama; Atefeh Sohrabizadeh; Jie Wang 022; Licheng Guo; Jason Cong (ACM Trans. Reconfigurable Technol. Syst., 2023)

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. - Licheng Guo; Yuze Chi; Jason Lau; Linghao Song; Xingyu Tian; Moazin Khatti; Weikang Qiao; Jie Wang 022; Ecenur Ustun; Zhenman Fang; Zhiru Zhang; Jason Cong (ACM Trans. Reconfigurable Technol. Syst., 2023)

PipeRAG: Fast Retrieval-Augmented Generation via Algorithm-System Co-design. - Wenqi Jiang 001; Shuai Zhang 007; Boran Han; Jie Wang 022; Bernie Wang 001; Tim Kraska (CoRR, 2024)

The Llama 3 Herd of Models. - Abhimanyu Dubey; Abhinav Jauhri; Abhinav Pandey; Abhishek Kadian; Ahmad Al-Dahle; Aiesha Letman; Akhil Mathur; Alan Schelten; Amy Yang; Angela Fan; Anirudh Goyal; Anthony Hartshorn; et al. (CoRR, 2024)

Scaling Llama 3 Training with Efficient Parallelism Strategies. - Weiwei Chu; Xinfeng Xie; Jiecao Yu; Jie Wang 022; Amar Phanishayee; Chunqiang Tang; Yuchen Hao; Jianyu Huang; Mustafa Ozdal; Jun Wang; Vedanuj Goswami; Naman Goyal 001; et al. (ISCA, 2025)

PipeRAG: Fast Retrieval-Augmented Generation via Adaptive Pipeline Parallelism. - Wenqi Jiang 001; Shuai Zhang 007; Boran Han; Jie Wang 022; Bernie Wang 001; Tim Kraska (KDD (1), 2025)

WLB-LLM: Workload-Balanced 4D Parallelism for Large Language Model Training. - Zheng Wang 075; Anna Cai; Xinfeng Xie; Zaifeng Pan; Yue Guan; Weiwei Chu; Jie Wang 022; Shikai Li; Jianyu Huang; Chris Cai; Yuchen Hao; Yufei Ding 001 (OSDI, 2025)