Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. - Jie Zhang 007; Nishant Patil; Subhasish Mitra (DATE, 2008)

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. - Nishant Patil; Albert Lin 002; Jie Zhang 007; H.-S. Philip Wong; Subhasish Mitra (DAC, 2009)

Carbon nanotube circuits in the presence of carbon nanotube density variations. - Jie Zhang 007; Nishant Patil; Arash Hazeghi; Subhasish Mitra (DAC, 2009)

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. - Shashikanth Bobba; Jie Zhang 007; Antonio Pullini; David Atienza; Giovanni De Micheli (DATE, 2009)

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. - Subhasish Mitra; Jie Zhang 007; Nishant Patil; Hai Wei (DATE, 2009)

Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. - Jie Zhang 007; Nishant Patil; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. - Jie Zhang 007; Shashikanth Bobba; Nishant Patil; Albert Lin 002; H.-S. Philip Wong; Giovanni De Micheli; Subhasish Mitra (DAC, 2010)

Carbon nanotube circuits: Living with imperfections and variations. - Jie Zhang 007; Nishant Patil; Albert Lin 002; H.-S. Philip Wong; Subhasish Mitra (DATE, 2010)

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. - Hai Wei; Jie Zhang 007; Lan Wei; Nishant Patil; Albert Lin 002; Max M. Shulaker; Hong-Yu Chen; H.-S. Philip Wong; Subhasish Mitra (ICCAD, 2011)

Robust System Design. - Subhasish Mitra; Hyungmin Cho; Ted Hong; Young Moon Kim; Hsiao-Heng Lee; Larkhoon Leem; Yanjing Li; David Lin; Evelyn Mintarno; Diana Mui; Sung-Boem Park; Nishant Patil; et al. (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. - Jie Zhang 007; Nishant Patil; Arash Hazeghi; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Carbon Nanotube Robust Digital VLSI. - Jie Zhang 007; Albert Lin 002; Nishant Patil; Hai Wei; Lan Wei; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. - Gage Hills; Jie Zhang 007; Charles Mackin; Max M. Shulaker; Hai Wei; H.-S. Philip Wong; Subhasish Mitra (DAC, 2013)

Carbon nanotube circuits: opportunities and challenges. - Hai Wei; Max M. Shulaker; Gage Hills; Hong-Yu Chen; Chi-Shuen Lee; Luckshitha Liyanage; Jie Zhang 007; H.-S. Philip Wong; Subhasish Mitra (DATE, 2013)

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. - Shashikanth Bobba; Jie Zhang 007; Pierre-Emmanuel Gaillardon; H.-S. Philip Wong; Subhasish Mitra; Giovanni De Micheli (ACM J. Emerg. Technol. Comput. Syst., 2014)

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. - Gage Hills; Jie Zhang 007; Max Marcel Shulaker; Hai Wei; Chi-Shuen Lee; Arjun Balasingam; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)