An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA. - Jie Zhang 038; Dongming Zhou (IEEE Trans. Instrum. Meas., 2018)

Frequency Stability-Aware Stochastic Modeling for Inter-System Bias in Multi-GNSS PPP. - Jinyang Han; Jie Zhang 038; Shiming Zhong; Xiaolong Mi; Daqian Lyu; Runmin Lu; Bibo Peng (IEEE Trans. Instrum. Meas., 2025)