Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. - Yazhuo Dong; Yong Dou; Jie Zhou 007 (ARC, 2007)

FPGA SAR Processor with Window Memory Accesses. - Yong Dou; Jie Zhou 007; Yuanwu Lei; Xingming Zhou (ASAP, 2007)

Multi-access memory architecture for image applications with multiple interested regions. - Jinbo Xu; Yong Dou; Jie Zhou 007 (APCCAS, 2008)

Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. - Jie Zhou 007; Yong Dou; Yuanwu Lei; Yazhuo Dong (ARC, 2008)

Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. - Jie Zhou 007; Yong Dou; Yuanwu Lei; Jinbo Xu; Yazhuo Dong (HPCC, 2008)

Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA. - Jie Zhou 007; Yazhuo Dong; Yong Dou; Yuanwu Lei (ICESS, 2008)

Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme. - Jinbo Xu; Yong Dou; Jie Zhou 007 (NAS, 2008)

A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. - Jie Zhou 007; Yong Dou; Jianxun Zhao; Fei Xia 003; Yuanwu Lei; Yuxing Tang (APPT, 2009)

A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. - Guiming Wu; Yong Dou; Yuanwu Lei; Jie Zhou 007; Miao Wang; Jingfei Jiang (FCCM, 2009)

FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. - Yong Dou; Jie Zhou 007; Xiaoyang Chen; Yuanwu Lei; Jinbo Xu (FPL, 2009)

FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. - Yong Dou; Yuanwu Lei; Guiming Wu; Song Guo 003; Jie Zhou 007; Li Shen (ICS, 2010)

A Unified Co-Processor Architecture for Matrix Decomposition. - Yong Dou; Jie Zhou 007; Guiming Wu; Jingfei Jiang; Yuanwu Lei; Shi-Ce Ni (J. Comput. Sci. Technol., 2010)

FPGA Implementation of Variable-Precision Floating-Point Arithmetic. - Yuanwu Lei; Yong Dou; Song Guo 003; Jie Zhou 007 (APPT, 2011)

VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic. - Yuanwu Lei; Yong Dou; Jie Zhou 007; Sufeng Wang (FPL, 2011)

Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. - Yuanwu Lei; Yong Dou; Li Shen; Jie Zhou 007; Song Guo 003 (ICCD, 2011)

A high-throughput reconfigurable Viterbi decoder. - Rongchun Li; Yong Dou; Jie Zhou 007; Guo-Qing Lei (WCSP, 2011)

FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic. - Yuanwu Lei; Yong Dou; Jie Zhou 007 (IEICE Trans. Inf. Syst., 2011)

A self-organizing and self-adaptive French flag Organism based on lateral activation model. - Jiaqing Xu; Qi Lv; Jie Zhou 007; Yong Dou (IEEE Congress on Evolutionary Computation, 2012)

A malicious code detection method based on statistical analysis. - Yunlong Wu; Chen Chen 016; Huiquan Wang; Jie Zhou 007; Xinhai Xu (FSKD, 2012)

A multi-standard efficient column-layered LDPC decoder for Software Defined Radio on GPUs. - Rongchun Li; Jie Zhou 007; Yong Dou; Song Guo 003; Dan Zou; Shi Wang (SPAWC, 2013)

Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access. - Lei Guo 029; Yuhua Tang; Yong Dou; Yuanwu Lei; Meng Ma; Jie Zhou 007 (IEICE Trans. Inf. Syst., 2013)

From WiFi to WiMAX: Efficient GPU-based Parameterized Transceiver across Different OFDM Protocols. - Rongchun Li; Yong Dou; Jie Zhou 007; Baofeng Li; Jinbo Xu (KSII Trans. Internet Inf. Syst., 2013)

VLIW coprocessor for IEEE-754 quadruple-precision elementary functions. - Yuanwu Lei; Yong Dou; Lei Guo 029; Jinbo Xu; Jie Zhou 007; Yazhuo Dong; Hongjian Li (ACM Trans. Archit. Code Optim., 2013)

FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic. - Yuanwu Lei; Yong Dou; Yazhuo Dong; Jie Zhou 007; Fei Xia 003 (J. Supercomput., 2013)

Transpose-free variable-size FFT accelerator based on-chip SRAM. - Lei Guo 029; Yuhua Tang; Yuanwu Lei; Yong Dou; Jie Zhou 007 (IEICE Electron. Express, 2014)

Efficient Parallel Interference Cancellation MIMO Detector for Software Defined Radio on GPUs. - Rongchun Li; Yong Dou; Jie Zhou 007; Chen Chen 016 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Design and Implement of High Performance Crypto Coprocessor. - Shi-Ce Ni; Yong Dou; Kai Chen 020; Jie Zhou 007 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

CuSora: Real-time software radio using multi-core graphics processing unit. - Rongchun Li; Yong Dou; Jie Zhou 007; Lin Deng; Shi Wang (J. Syst. Archit., 2014)

Hyperspectral image classification via kernel extreme learning machine using local receptive fields. - Qi Lv; Xin Niu 002; Yong Dou; Yueqing Wang; Jiaqing Xu; Jie Zhou 007 (ICIP, 2016)