A 100-MHz pipelined CMOS comparator. - Jieh-Tsorng Wu; Bruce A. Wooley (IEEE J. Solid State Circuits, 1988)

A two-chip 1.5-GBd serial link interface. - Richard C. Walker; Cheryl L. Stout; Jieh-Tsorng Wu; Benny Lai; Chu-Sun Yen; Thomas Hornak; Patrick T. Petruno (IEEE J. Solid State Circuits, 1992)

A 2 V 1.6 GHz BJT phase-locked loop. - Wei-Zen Chen; Jieh-Tsorng Wu (CICC, 1998)

A 2-V 2-GHz BJT variable frequency oscillator. - Wei-Zen Chen; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 1998)

MOS charge pumps for low-voltage operation. - Jieh-Tsorng Wu; Kuen-Long Chang (IEEE J. Solid State Circuits, 1998)

A 2-V, 1.8-GHz BJT phase-locked loop. - Wei-Zen Chen; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 1999)

Highly linear 100 MHz CMOS programmable gain amplifiers. - Cheng-Chung Hsu; Jieh-Tsorng Wu (ISCAS (1), 2001)

A digital background calibration technique for pipelined analog-to-digital converters. - Hung-Chih Liu; Zwei-Mei Lee; Jieh-Tsorng Wu (ISCAS (1), 2003)

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier. - Cheng-Chung Hsu; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2003)

Multi-level memory systems using error control codes. - Hsie-Chia Chang; Chien-Ching Lin; Tien-Yuan Hsiao; Jieh-Tsorng Wu; Ta-Hui Wang (ISCAS (2), 2004)

A statistical background calibration technique for flash analog-to-digital converters. - Chun-Cheng Huang; Jieh-Tsorng Wu (ISCAS (1), 2004)

A robust background calibration technique for switched-capacitor pipelined ADCs. - Jen-Lin Fan; Jieh-Tsorng Wu (ISCAS (2), 2005)

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. - Hung-Chih Liu; Zwei-Mei Lee; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2005)

Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration". - Hung-Chih Liu; Zwei-Mei Lee; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2005)

A background comparator calibration technique for flash analog-to-digital converters. - Chun-Cheng Huang; Jieh-Tsorng Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation. - Ju-Ming Chou; Yu-Tang Hsieh; Jieh-Tsorng Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A background timing-skew calibration technique for time-interleaved analog-to-digital converters. - Chung-Yi Wang; Jieh-Tsorng Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration. - Zwei-Mei Lee; Cheng-Yeh Wang; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2007)

A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs. - Jen-Lin Fan; Chung-Yi Wang; Jieh-Tsorng Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection. - Chung-Yi Wang; Jieh-Tsorng Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Jitter Measurement and Compensation for Analog-to-Digital Converters. - Chi-Wei Fan; Jieh-Tsorng Wu (IEEE Trans. Instrum. Meas., 2009)

ADC clock jitter measurement and correction using a stochastic TDC. - Chi-Wei Fan; Jieh-Tsorng Wu (APCCAS, 2010)

A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. - Yung-Hui Chung; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2010)

A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. - Wei-Hsin Tseng; Chi-Wei Fan; Jieh-Tsorng Wu (ISSCC, 2011)

A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques. - Chun-Cheng Huang; Chung-Yi Wang; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2011)

A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz. - Wei-Hsin Tseng; Chi-Wei Fan; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2011)

A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero. - Wei-Hsin Tseng; Jieh-Tsorng Wu; Yung-Cheng Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps. - Bing-Nan Fang; Jieh-Tsorng Wu (ISCAS, 2012)

A 5.37mW 10b 200MS/s dual-path pipelined ADC. - Yun Chai; Jieh-Tsorng Wu (ISSCC, 2012)

A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC. - Yun Chai; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2012)

A 1-V 100-dB dynamic range 24.4-kHz bandwidth delta-sigma modulator. - Chia-Ling Chang; Jieh-Tsorng Wu (ISCAS, 2013)

F6: Mixed-signal/RF design and modeling in next-generation CMOS. - Boris Murmann; Jafar Savoj; Piet Wambacq; Jieh-Tsorng Wu (ISSCC, 2013)

Background calibration of integrator leakage in discrete-time delta-sigma modulators. - Su-Hao Wu; Jieh-Tsorng Wu (NEWCAS, 2013)

A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation. - Bing-Nan Fang; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2013)

A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. - Su-Hao Wu; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2013)

Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. - Makoto Takamiya; Jieh-Tsorng Wu; Jussi Ryynänen; Kenichi Okada 001; Jaeha Kim (IEEE J. Solid State Circuits, 2015)

A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. - Yung-Hui Chung; Jieh-Tsorng Wu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A computationally-efficient PWM technique for digital class-D amplifiers. - Chih-Min Chang; Jieh-Tsorng Wu (ISCAS, 2016)

A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter. - Chih-Min Chang; Jieh-Tsorng Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques. - Sheng-Hui Liao; Jieh-Tsorng Wu (CICC, 2018)

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. - Eric Swindlehurst; Hunter Jensen; Alexander Petrie; Yixin Song; Yen-Cheng Kuan; Mau-Chung Frank Chang; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang (ESSCIRC, 2019)

A 1-V 175- $ mu$ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques. - Sheng-Hui Liao; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2019)

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. - Eric Swindlehurst; Hunter Jensen; Alexander Petrie; Yixin Song; Yen-Cheng Kuan; Yong Qu; Mau-Chung Frank Chang; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang (IEEE J. Solid State Circuits, 2021)

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. - Cheng-Yu Chiang; Chia-Lin Hu; Mark Po-Hung Lin; Yu-Szu Chung; Shyh-Jye Jou; Jieh-Tsorng Wu; Shiuh-Hua Wood Chiang; Chien-Nan Jimmy Liu; Hung-Ming Chen (ASP-DAC, 2023)

A Digital Jitter Compensation Technique for Analog-to-Digital Converters. - Ding-Hao Wang; Jieh-Tsorng Wu (ISCAS, 2023)