A SIMD multiplier-accumulator design for pairing cryptography. - Weizhen Wang; Jun Han 003; Jielin Wang; Xiaoyang Zeng (ASICON, 2015)

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. - Jielin Wang; Weizhen Wang; Jianwei Yang; Zhiyi Yu; Jun Han 003; Xiaoyang Zeng (ASICON, 2015)

Countering power analysis attacks by exploiting characteristics of multicore processors. - Jianwei Yang; Fan Dai; Jielin Wang; Jianmin Zeng; Zhang Zhang 004; Jun Han 003; Xiaoyang Zeng (IEICE Electron. Express, 2018)

Instrument Pointer Recognition Scheme Based on Improved CSL Algorithm. - Hailong Liu; Jielin Wang; Bo Ma (Sensors, 2022)