3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology. - Aporva Amarnath; Javad Bagherzadeh; Jielun Tan; Ronald G. Dreslinski (ISLPED, 2019)

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. - Subhankar Pal; Dong-Hyeon Park; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (VLSI Circuits, 2019)

R2D3: A Reliability Engine for 3D Parallel Systems. - Javad Bagherzadeh; Aporva Amarnath; Jielun Tan; Subhankar Pal; Ronald G. Dreslinski (DAC, 2020)

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. - Dong-Hyeon Park; Subhankar Pal; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (IEEE J. Solid State Circuits, 2020)

RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA. - Stephen A. Zekany; Jielun Tan; James A. Connelly; Ronald G. Dreslinski (SIGCSE, 2021)

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. - Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan-Yu Chen 001; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong 002; Trevor N. Mudge; Chaitali Chakrabarti; David T. Blaauw; Ronald G. Dreslinski; et al. (VLSI Circuits, 2021)

Teaching Out-of-Order Processor Design with the RISC-V ISA. - Stephen A. Zekany; Jielun Tan; James A. Connolly (WCAE, 2021)

A Holistic Solution for Reliability of 3D Parallel Systems. - Javad Bagherzadeh; Aporva Amarnath; Jielun Tan; Subhankar Pal; Ronald G. Dreslinski (ACM J. Emerg. Technol. Comput. Syst., 2022)

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. - Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan-Yu Chen 001; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong 002; Trevor N. Mudge; Chaitali Chakrabarti; David T. Blaauw; Ronald G. Dreslinski; et al. (IEEE J. Solid State Circuits, 2022)