A new test and characterization scheme for 10+ GHz low jitter wide band PLL. - Kazuhiko Miki; David Boerstler; Eskinder Hailu; Jieming Qi; Sarah Pettengill; Yuichi Goto (ASP-DAC, 2006)

A Circuit for Reducing Large Transient Current Effects on Processor Power Grids. - Eskinder Hailu; David W. Boerstler; Kazuhiko Miki; Jieming Qi; Michael Wang 001; Mack W. Riley (ISSCC, 2006)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)