NoC frequency scaling with flexible-pipeline routers. - Pingqiang Zhou; Jieming Yin; Antonia Zhai; Sachin S. Sapatnekar (ISLPED, 2011)

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. - Jieming Yin; Pingqiang Zhou; Anup Holey; Sachin S. Sapatnekar; Antonia Zhai (ISLPED, 2012)

Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems. - Jieming Yin; Pingqiang Zhou; Sachin S. Sapatnekar; Antonia Zhai (IPDPS, 2014)

Efficient synthetic traffic models for large, complex SoCs. - Jieming Yin; Onur Kayiran; Matthew Poremba; Natalie D. Enright Jerger; Gabriel H. Loh (HPCA, 2016)

There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. - Matthew Poremba; Itir Akgun; Jieming Yin; Onur Kayiran; Yuan Xie 001; Gabriel H. Loh (ISCA, 2017)

Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level. - Anthony Gutierrez; Bradford M. Beckmann; Alexandru Dutu; Joseph Gross; Michael LeBeane; John Kalamatianos; Onur Kayiran; Matthew Poremba; Brandon Potter; Sooraj Puthoor; Matthew D. Sinclair; Mark Wyse; et al. (HPCA, 2018)

Modular Routing Design for Chiplet-Based Systems. - Jieming Yin; Zhifeng Lin; Onur Kayiran; Matthew Poremba; Muhammad Shoaib Bin Altaf; Natalie D. Enright Jerger; Gabriel H. Loh (ISCA, 2018)

Northup: Divide-and-Conquer Programming in Systems with Heterogeneous Memories and Processors. - Shuai Che; Jieming Yin (IPDPS, 2019)

An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems. - Xiangwei Cai; Jieming Yin; Pingqiang Zhou (Integr., 2019)

Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling. - Srikant Bharadwaj; Jieming Yin; Bradford M. Beckmann; Tushar Krishna (DAC, 2020)

Experiences with ML-Driven Design: A NoC Case Study. - Jieming Yin; Subhash Sethumurugan; Yasuko Eckert; Chintan Patel; Alan Smith 003; Eric Morton; Mark Oskin; Natalie D. Enright Jerger; Gabriel H. Loh (HPCA, 2020)

In-Network Memory Access Ordering for Heterogeneous Multicore Systems. - Jieming Yin; Antonia Zhai (NOCS, 2020)

Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC. - Yuan Zhou; Hanyu Wang 005; Jieming Yin; Zhiru Zhang (DAC, 2021)

Designing a Cost-Effective Cache Replacement Policy using Machine Learning. - Subhash Sethumurugan; Jieming Yin; John Sartori (HPCA, 2021)

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. - Liqiang Lu; Naiqing Guan; Yuyue Wang 001; Liancheng Jia; Zizhang Luo; Jieming Yin; Jason Cong; Yun Liang 001 (ISCA, 2021)

Improving Address Translation in Multi-GPUs via Sharing and Spilling aware TLB Design. - Bingyao Li; Jieming Yin; Youtao Zhang; Xulong Tang (MICRO, 2021)

CryptoGCN: Fast and Scalable Homomorphically Encrypted Graph Convolutional Network Inference. - Ran Ran; Wei Wang; Quan Gang; Jieming Yin; Nuo Xu; Wujie Wen (NeurIPS, 2022)

Design Challenges of Intrachiplet and Interchiplet Interconnection. - Chixiao Chen; Jieming Yin; Yarui Peng; Maurizio Palesi; Wenxu Cao; Letian Huang; Amit Kumar Singh 002; Haocong Zhi; Xiaohang Wang 001 (IEEE Des. Test, 2022)

Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. - Zizhang Luo; Liqiang Lu; Size Zheng 001; Jieming Yin; Jason Cong; Jianwei Yin; Yun Liang 001 (DAC, 2023)

Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding. - Bingyao Li; Jieming Yin; Anup Holey; Youtao Zhang; Jun Yang 002; Xulong Tang (HPCA, 2023)

Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators. - Xiaochen Hao; Zijian Ding; Jieming Yin; Yuan Wang 001; Yun Liang 001 (ICCAD, 2023)

COLA: Orchestrating Error Coding and Learning for Robust Neural Network Inference Against Hardware Defects. - Anlan Yu; Ning Lyu; Jieming Yin; Zhiyuan Yan; Wujie Wen (ICML, 2023)

CompoundEye: A 0.24-4.17 TOPS Scalable Multi-Node DNN Processor for Image Recognition. - Xiaobai Chen; Qiurun Hu; Fu Xiao 001; Jieming Yin (ISCAS, 2023)

QuCT: A Framework for Analyzing Quantum Circuit by Extracting Contextual and Topological Features. - Siwei Tan; Congliang Lang; Liang Xiang; Shudi Wang; Xinghui Jia; Ziqi Tan; Tingting Li 004; Jieming Yin; Yongheng Shang; Andre Python; Liqiang Lu; Jianwei Yin (MICRO, 2023)

NeuroPots: Realtime Proactive Defense against Bit-Flip Attacks in Neural Networks. - Qi Liu 017; Jieming Yin; Wujie Wen; Chengmo Yang; Shi Sha (USENIX Security Symposium, 2023)

ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators. - Xiaochen Hao; Zijian Ding; Jieming Yin; Yuan Wang 001; Yun Liang 001 (CoRR, 2023)

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. - Liqiang Lu; Zizhang Luo; Size Zheng 001; Jieming Yin; Jason Cong; Yun Liang 001; Jianwei Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

CoupledCB: Eliminating Wasted Pages in Copyback-based Garbage Collection for SSDs. - Jun Li 062; Xiaofei Xu; Zhibing Sha; Xiaobai Chen; Jieming Yin; Jianwei Liao 001 (DATE, 2025)

CAMC: A Multi-Chiplet Accelerator With Heterogeneous Memory-Based Computing Architecture For DNN Training. - Xiaobai Chen; Hao Dong; Jiacheng Mei; Jun Li; Yifei Tian; Jieming Yin; Fu Xiao 001 (ISCAS, 2025)

DPAcc: An FPGA-based Differential Privacy Acceleration Framework. - Ao Dong; Yuxiang Wang; Pengyang Li; Yifei Tian; Xiaobai Chen; Jieming Yin (ISCAS, 2025)

FlexAcc: Accelerating Batch Normalization through GPU-FPGA Integration. - Haishuai Zhang; Zhihao Li; Pengyang Li; Xuehuai Shi; Xiaobai Chen; Jieming Yin (ISCAS, 2025)