The design of fast totally self-checking Berger code checkers based on Berger code partitioning. - Jien-Chung Lo; Suchai Thanawastien (FTCS, 1988)

Concurrent error detection in arithmetic and logical operations using Berger codes. - Jien-Chung Lo; Suchai Thanawastien; T. R. N. Rao (IEEE Symposium on Computer Arithmetic, 1989)

On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. - Jien-Chung Lo; Suchai Thanawastien (IEEE Trans. Computers, 1990)

A new protocol for efficient bandwidth distribution in integrated service networks. - Hungshih Chang; Jien-Chung Lo (LCN, 1991)

Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing. - Jien-Chung Lo; James C. Daly; Michael Nicolaidis (FTCS, 1992)

Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. - Jien-Chung Lo (ICCD, 1992)

On-chip current sensing circuit for CMOS VLSI. - Tung-Li Shen; James C. Daly; Jien-Chung Lo (VTS, 1992)

An SFS Berger check prediction ALU and its application to self-checking processor designs. - Jien-Chung Lo; Suchai Thanawastien; T. R. N. Rao; Michael Nicolaidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A Probabilistic Measurement for Totally Self-Checking Circuits. - Jien-Chung Lo; Eiji Fujiwara (DFT, 1993)

Fault-Tolerant Content Addressable Memory. - Jien-Chung Lo (ICCD, 1993)

Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. - T. R. N. Rao; Gui Liang Feng; Mahadev S. Kolluru; Jien-Chung Lo (IEEE Trans. Computers, 1993)

A 2-ns detecting time, 2- mu m CMOS built-in current sensing circuit. - Tung-Li Shen; James C. Daly; Jien-Chung Lo (IEEE J. Solid State Circuits, 1993)

Novel area-time efficient static CMOS totally self-checking comparator. - Jien-Chung Lo (IEEE J. Solid State Circuits, 1993)

Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. - Jien-Chung Lo (IEEE Trans. Computers, 1994)

A concurrent error detection IC in 2-μm static CMOS logic. - Jien-Chung Lo; Shih-Yao Sun; James C. Daly (IEEE J. Solid State Circuits, 1994)

Single fault masking logic designs with error correcting codes. - Jien-Chung Lo (DFT, 1995)

A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations. - Jien-Chung Lo; James C. Daly; Michael Nicolaidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. - Jien-Chung Lo; Masato Kitakami; Eiji Fujiwara (DFT, 1996)

Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library. - Peilin Song; Jien-Chung Lo (DFT, 1996)

A Hyper Optimal Encoding Scheme for Self-Checking Circuits. - Jien-Chung Lo (IEEE Trans. Computers, 1996)

Probability to Achieve TSC Goal. - Jien-Chung Lo; Eiji Fujiwara (IEEE Trans. Computers, 1996)

Berger Check Prediction for Array Multipliers and Array Dividers. - Jien-Chung Lo; Suchai Thanawastien; T. R. N. Rao (IEEE Trans. Computers, 1996)

Fast and area-time efficient Berger code checkers. - Yu-Yau Guo; Jien-Chung Lo; Cecilia Metra (DFT, 1997)

A Fast Binary Adder with Conditional Carry Generation. - Jien-Chung Lo (IEEE Trans. Computers, 1997)

Challenges of Built-In Current Sensor Designs. - Yu-Yau Guo; Jien-Chung Lo (DFT, 1998)

Highly Reliable Systems with Differential Built-In Current Sensors. - Jien-Chung Lo (DFT, 1998)

Online Current Testing. - Jien-Chung Lo (IEEE Des. Test Comput., 1998)

Correction to "A Fast Binary Adder with Conditional Carry Generation" IEEE Transaction on Computers 46(2) 248-253 (1997). - Jien-Chung Lo (IEEE Trans. Computers, 1998)

A Case Study of Self-Checking Circuits Reliability. - Jien-Chung Lo (VLSI Design, 1998)

Erasure Error Correction with Hardware Detection. - William D. Armitage; Jien-Chung Lo (DFT, 1999)

The 2nd Order Analysis of IDDQ Test Data. - Shengli Li; Kai Zhang; Jien-Chung Lo (DFT, 2000)

Intermediacy Prediction for High Speed Berger Code Checkers. - Cecilia Metra; Jien-Chung Lo (J. Electron. Test., 2000)

Building Real Computer Systems. - Augustus K. Uht; Jien-Chung Lo; Ying Sun; James C. Daly; James Kowalski (IEEE Micro, 2000)

Efficient Parity Prediction in FPGA. - Seok-Bum Ko; Tian Xia; Jien-Chung Lo (DFT, 2001)

Using Atomic Force Microscopy for Deep-Submicron Failure Analysis. - Jien-Chung Lo; William D. Armitage; Corbet S. Johnson (IEEE Des. Test Comput., 2001)

On-Chip Jitter Measurement for Phase Locked Loops. - Tian Xia; Jien-Chung Lo (DFT, 2002)

Efficient Decomposition Techniques for FPGAs. - Seok-Bum Ko; Jien-Chung Lo (HiPC, 2002)

Studies of the SEMATECH IDDq test data. - Seok-Bum Ko; Yu-Yau Guo; Jien-Chung Lo (J. Syst. Archit., 2002)

Analysis of a BICS-Only Concurrent Error Detection Method. - Jien-Chung Lo (IEEE Trans. Computers, 2002)

On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. - Tian Xia; Jien-Chung Lo (Asian Test Symposium, 2003)

A Novel Technology Mapping Method for AND/XOR Expressions. - Seok-Bum Ko; Jien-Chung Lo (ISMVL, 2003)

Time-to-voltage converter for on-chip jitter measurement. - Tian Xia; Jien-Chung Lo (IEEE Trans. Instrum. Meas., 2003)

Delay chain based programmable jitter generator. - Tian Xia; Peilin Song; Keith A. Jenkins; Jien-Chung Lo (ETS, 2004)

Efficient Realization of Parity Prediction Functions in FPGAs. - Seok-Bum Ko; Jien-Chung Lo (J. Electron. Test., 2004)

Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. - Jien-Chung Lo; Yu-Lun Wan; Eiji Fujiwara (DFT, 2005)

On-chip short-time interval measurement system for high-speed signal timing characterization. - Tian Xia; Jien-Chung Lo (J. Syst. Archit., 2005)

Equivalent IDDQ Tests for Systems with Regulated Power Supply. - Chuen-Song Chen; Jien-Chung Lo; Tian Xia (DFT, 2006)

An indirect current sensing technique for IDDQ and IDDT tests. - Chuen-Song Chen; Jien-Chung Lo; Tian Xia (ACM Great Lakes Symposium on VLSI, 2006)

Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). - Jien-Chung Lo; Cecilia Metra; Fabrizio Lombardi (IEEE Trans. Computers, 2006)