10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. - Wei-Han Cho; Yilei Li; Yuan Du; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Sheau Jiung Lee; Huan-Neng Ron Chen; Chewnpu Jou; Fu-Lung Hsueh; Mau-Chung Frank Chang (ISSCC, 2016)

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. - Yuan Du; Wei-Han Cho; Yilei Li; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Yanghyo Kim; Zuow-Zun Chen; Sheau Jiung Lee; Mau-Chung Frank Chang (VLSI Circuits, 2016)

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection. - Yuan Du; Wei-Han Cho; Po-Tsang Huang; Yilei Li; Chien-Heng Wong; Jieqiong Du; Yanghyo Kim; Boyu Hu; Li Du; Chun-Chen Liu; Sheau Jiung Lee; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2017)

High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. - Weikang Qiao; Jieqiong Du; Zhenman Fang; Michael Lo; Mau-Chung Frank Chang; Jason Cong (FCCM, 2018)

High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only). - Weikang Qiao; Jieqiong Du; Zhenman Fang; Libo Wang; Michael Lo; Mau-Chung Frank Chang; Jason Cong (FPGA, 2018)

Nondestructive Image De-Blurring Based on Diffraction Blurring Model. - Yangjie Wei; Jieqiong Du; Yongjun Liu (ROBIO, 2018)

A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. - X. Shawn Wang; Xin Jin; Jieqiong Du; Yilei Li; Yuan Du; Chien-Heng Wong; Yen-Cheng Kuan; Chi-Hang Chan; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. - Jieqiong Du; Chien-Heng Wong; Yo-Hao Tu; Wei-Han Cho; Yilei Li; Yuan Du; Po-Tsang Huang; Sheau Jiung Lee; Mau-Chung Frank Chang (NOCS, 2019)

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT). - Yuan Du; Li Du; Xuefeng Gu; Jieqiong Du; X. Shawn Wang; Boyu Hu; Mingzhe Jiang; Xiaoliang Chen; Subramanian S. Iyer; Mau-Chung Frank Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface. - Jieqiong Du; Jia Zhou; Chia-Jen Liang; Boyu Hu; Yuan Du; Mau-Chung Frank Chang (VLSI Circuits, 2020)

A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology. - Dong-Myung Choi; Yikui Dong; Roan Nicholson; Frank Liu 008; Wenyan Jia; Vadim Levin; Mike He; Sameer Pradhan; Jieqiong Du; Michael De Vita; Amanda Tran; Reza Navid; et al. (VLSI Technology and Circuits, 2024)