Design Considerations of Monolithically Integrated Voltage Regulators for Multicore Processors. - Hesam Fathi Moghadam; Jieun Jang; Michael Dayringer; Thipok Rak-amnouykit; Guanghua Shu; Anatoly Yakovlev; Yue Zhang; David Hopkins 001 (ISCAS, 2018)

A 0.53pJK2 7000μm2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS. - Woojun Choi; Yong-Tae Lee; Seonhong Kim; Sanghoon Lee 009; Jieun Jang; Junhyun Chun; Kofi A. A. Makinwa; Youngcheol Chae (ISSCC, 2018)

A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy. - Seokbo Shim; Sungho Kim; Jooyoung Bae; Keunsik Ko; Eunryeong Lee; Kwidong Kim; Kyeongtae Kim; Sangho Lee; Jinhoon Hyun; Insung Koh; Joonhong Park; Minjeong Kim; et al. (ISSCC, 2018)

A Compact Resistor-Based CMOS Temperature Sensor With an Inaccuracy of 0.12 °C (3σ) and a Resolution FoM of 0.43 pJ⋅K2 in 65-nm CMOS. - Woojun Choi; Yong-Tae Lee; Seonhong Kim; Sanghoon Lee 009; Jieun Jang; Junhyun Chun; Kofi A. A. Makinwa; Youngcheol Chae (IEEE J. Solid State Circuits, 2018)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. - Jihyo Kang; Jaehyeok Yang; Kyunghoon Kim; Joo-Hyung Chae; Gang-Sik Lee; Sang-Yeon Byeon; Boram Kim; Dong-Hyun Kim; Youngtaek Kim; Yeongmuk Cho; Junghwan Ji; Sera Jeong; et al. (IEEE J. Solid State Circuits, 2022)

A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. - Soyeong Shin; Yongjae Lee; Jiheon Park; Jihyo Kang; Kyunghoon Kim; Dae-Han Kwon; Sangkwon Lee; Jieun Jang; Joo-Hwan Cho; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. - Dae-Han Kwon; Seongju Lee; Kyuyoung Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dongyoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; et al. (IEEE J. Solid State Circuits, 2023)

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)