Instruction Cache Prefetching with Extended BTB. - Shyh-An Chi; R.-Ming Shiu; Jih-Ching Chiu; Si-En Chang; Chung-Ping Chung (ICPADS, 1997)

Design of Instruction Stream Buffer with Trace Support for X86 Processors. - Jih-Ching Chiu; I-Huan Huang; Chung-Ping Chung (ICCD, 2000)

Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. - Jih-Ching Chiu; Michael Jin-Yi Wang; Chung-Ping Chung (J. Inf. Sci. Eng., 2002)

Variable-size data item placement for load and storage balancing. - Yung-Cheng Ma; Jih-Ching Chiu; Tien-Fu Chen; Chung-Ping Chung (J. Syst. Softw., 2003)

FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit. - Jih-Ching Chiu; Ren-Bang Lin (Asia-Pacific Computer Systems Architecture Conference, 2005)

Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. - Jih-Ching Chiu; Yu-Liang Chou; Ta-Li Yeh; Tseng-Kuei Lin (ACSAC, 2008)

The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. - Jih-Ching Chiu; Yu-Liang Chou; Ren-Bang Lin (J. Inf. Sci. Eng., 2008)

A multi-streaming SIMD architecture for multimedia applications. - Jih-Ching Chiu; Yu-Liang Chou; Hua-Yi Tzeng (Conf. Computing Frontiers, 2009)

The Software and Hardware Integration Linker for Reconfigurable Embedded System. - Jih-Ching Chiu; Ta-Li Yeh; Mun-Kit Leong (CSE (2), 2009)

The Rendezvous Mechanism for the Multi-core AMBA System. - Jih-Ching Chiu; Kai-Ming Yang; Mu-Chi Chang (ICPP Workshops, 2009)

Design of a novel SIMD architecture by fusing operations and registers. - Jih-Ching Chiu; Kai-Ming Yang; Yu-Liang Chou (ICS, 2009)

A hyperscalar multi-core architecture. - Jih-Ching Chiu; Yu-Liang Chou; Ding-Siang Su (Conf. Computing Frontiers, 2010)

Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. - Jih-Ching Chiu; Yu-Liang Chou; Po-Kai Chen (ICPP, 2010)

A Novel instruction stream buffer for VLIW architectures. - Jih-Ching Chiu; Kai-Ming Yang (Comput. Electr. Eng., 2010)

IRES: An integrated software and hardware interface framework for reconfigurable embedded system. - Jih-Ching Chiu; Ta-Li Yeh (IET Comput. Digit. Tech., 2010)

The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. - Jih-Ching Chiu; Yu-Liang Chou; Tseng-Kuei Lin (J. Inf. Sci. Eng., 2010)

A multi-streaming SIMD multimedia computing engine. - Jih-Ching Chiu; Yu-Liang Chou (Microprocess. Microsystems, 2010)

A Unitable Computing Architecture for Chip Multiprocessors. - Jih-Ching Chiu; Yu-Liang Chou; Po-Kai Chen; Ding-Siang Su (Comput. J., 2011)

Analytical Modeling for Multi-transaction Bus on Distributed Systems. - Jih-Ching Chiu; Kai-Ming Yang; Chen-Ang Wong (ICA3PP (2), 2012)

High-speed low-power multiplexer-based selector for priority policy. - Jih-Ching Chiu; Kai-Ming Yang (Comput. Electr. Eng., 2013)

A relation-exchanging buffering mechanism for instruction and data streaming. - Jih-Ching Chiu; Kai-Ming Yang; Yu-Liang Chou; Chih-Kang Wu (Comput. Electr. Eng., 2013)

A hyperscalar dual-core architecture for embedded systems. - Jih-Ching Chiu; Kai-Ming Yang; Yu-Liang Chou (Microprocess. Microsystems, 2013)

Two-Dimensional Interpolation-Assisted Channel Prediction for OFDM Systems. - Hsuan-Chang Lee; Jih-Ching Chiu; Ken-Huang Lin (IEEE Trans. Broadcast., 2013)

Design and implementation of sequential repair and backup routing protocol for wireless mesh network. - Jih-Ching Chiu; Chun-Yao Zheng; Yao-Chin Huang; Kai-Ming Yang (ICNC, 2014)

Linked List Routing Algorithm with Wormhole Mechanism for Data Collecting Wireless Network. - Jih-Ching Chiu; Wen-Shin Wang; Chien-Lung Chen (ICS, 2014)

Design and Implementation of Tree Topology Algorithm for Power Line Communication Network. - Guan-Jen Huang; Jih-Ching Chiu; Yueh-Lin Li (ICS, 2018)

Adaptive Linked-List Mechanism for Wi-Fi Wireless Network. - Tsung-Lin Lee; Jih-Ching Chiu; Yueh-Lin Li (ICS, 2018)

Design of Instruction Analyzer with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. - Yi-Xuan Lu; Jih-Ching Chiu; Shu-Jung Chao; Yong-Bin Ye (ICS, 2018)

Design and Implement Robust Wireless Network Based on TCP Protocol. - Jih-Ching Chiu; Jun-Jiang Chen; Kuan-Lun Su (ICS, 2020)

Design and Implement Adaptive Tree Topology Mechanism For Wi-Fi Wireless Network. - Jih-Ching Chiu; Cheng-Lin Tsai; Zhi-Yu Lee (ICS, 2020)

Design of Multidimension-media Streaming Protocol Based on RTSP. - Jih-Ching Chiu; Hao-Yu Tseng; Zhi-Yu Lee (ICS, 2020)

The Brain Memory Architecture HW/SW Co-Design Platform with Adaptive CNN Algorithm. - Jih-Ching Chiu; Yu-Yi Wang; Wei-Yi Lin (ICS, 2020)

Design and Implementation of the Optimized Computing Architecture for Matrix Decomposition Algorithms. - Jih-Ching Chiu; Yu-Quen Chen; Yi-Xiang Wang; Yung-Chi Liu (ICS, 2022)

Design and Implementation of the Link-List DMA Controller for High Bandwidth Data Streaming. - Jih-Ching Chiu; Yan-Ting Wu; Yung-Chi Liu; Chi-Yang Hsieh (ICS, 2022)

Design and Implementation of the CNN Accelator Based on Multi-streaming SIMD Mechanisms. - Jih-Ching Chiu; Zhe-You Yan; Yung-Chi Liu (ICS, 2022)