Using a single input to support multiple scan chains. - Kuen-Jong Lee; Jih-Jeen Chen; Cheng-Hua Huang (ICCAD, 1998)

Broadcasting test patterns to multiple circuits. - Kuen-Jong Lee; Jih-Jeen Chen; Cheng-Hua Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Peak-power reduction for multiple-scan circuits during test application. - Kuen-Jong Lee; Tsung-Chu Huang; Jih-Jeen Chen (Asian Test Symposium, 2000)

Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. - Kuen-Jong Lee; Jih-Jeen Chen (Asian Test Symposium, 2002)

Test pattern generation and clock disabling for simultaneous test time and power reduction. - Jih-Jeen Chen; Chia-Kai Yang; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)