FAME: A Fault-Pattern Based Memory Failure Analysis Framework. - Kuo-Liang Cheng; Chih-Wea Wang; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu (ICCAD, 2003)

Fault Pattern Oriented Defect Diagnosis for Memories. - Chih-Wea Wang; Kuo-Liang Cheng; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu; Frank Huang; Hong-Tzer Yang (ITC, 2003)

A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. - Hsiang-Huang Wu; Jih-Nung Lee; Ming-Cheng Chiang; Po-Wei Liu; Chi-Feng Wu (ITC, 2009)

Case study of yield learning through in-house flow of volume diagnosis. - Pei-Ying Hsueh; Shuo-Fen Kuo; Chao-Wen Tzeng; Jih-Nung Lee; Chi-Feng Wu (VLSI-DAT, 2013)

Physical-aware systematic multiple defect diagnosis. - Po-Juei Chen; Chieh-Chih Che; J. C.-M. Li; Shuo-Fen Kuo; Pei-Ying Hsueh; Chun-Yi Kuo; Jih-Nung Lee (IET Comput. Digit. Tech., 2014)

Case study of process and design performance debugging with Digital Speed Sensor. - Chao-Wen Tzeng; Yin-Yen Chen; Jih-Nung Lee; Shu-Yi Kao (VLSI-DAT, 2015)

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique. - Chih-Ying Tsai; Kao-Chi Lee; Chien-Hsueh Lin; Sung-Chu Yu; Wen-Rong Liau; Alex Chun-Liang Hou; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Mango C.-T. Chao (VTS, 2016)

Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques. - Tzu-Hsuan Huang; Wei-Tse Hung; Hao-Yu Yang; Wen-Hsiang Chang; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Mango C.-T. Chao (ASP-DAC, 2017)

Methodology of generating dual-cell-aware tests. - Yu-Hao Huang; Ching-Ho Lu; Tse-Wei Wu; Yu-Teng Nien; Ying-Yen Chen; Max Wu; Jih-Nung Lee; Mango C.-T. Chao (VTS, 2017)

A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement. - Chien-Hsueh Lin; Chih-Ying Tsai; Kao-Chi Lee; Sung-Chu Yu; Wen-Rong Liau; Alex Chun-Liang Hou; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Mango C.-T. Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Layout-Based Dual-Cell-Aware Tests. - Tse-Wei Wu; Dong-Zhen Lee; Yu-Hao Huang; Mango C.-T. Chao; Kai-Chiang Wu; Shu-Yi Kao; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee (VTS, 2019)

CNN-based Stochastic Regression for IDDQ Outlier Identification. - Chun-Teng Chen; Chia-Heng Yen; Cheng-Yen Wen; Cheng-Hao Yang; Kai-Chiang Wu; Mason Chern; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (VTS, 2020)

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. - Cheng-Hao Yang; Chia-Heng Yen; Ting-Rui Wang; Chun-Teng Chen; Mason Chern; Ying-Yen Chen; Jih-Nung Lee; Shu-Yi Kao; Kai-Chiang Wu; Mango Chia-Tso Chao (VTS, 2021)

Methodology of Generating Timing-Slack-Based Cell-Aware Tests. - Yu-Teng Nien; Kai-Chiang Wu; Dong-Zhen Lee; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

CNN-Based Stochastic Regression for IDDQ Outlier Identification. - Chia-Heng Yen; Chun-Teng Chen; Cheng-Yen Wen; Ying-Yen Chen; Jih-Nung Lee; Shu-Yi Kao; Kai-Chiang Wu; Mango Chia-Tso Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)