An area- and power-efficient half-rate clock and data recovery circuit. - Yen-Long Lee; Soon-Jyh Chang; Rong-Sing Chu; Yen-Chi Chen; Jih Ren Goh; Chung-Ming Huang (ISCAS, 2014)

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. - Jih Ren Goh; Yen-Long Lee; Soon-Jyh Chang (VLSI-DAT, 2015)

A low power duobinary voltage mode transmitter. - Ming-Hung Chien; Yen-Long Lee; Jih Ren Goh; Soon-Jyh Chang (ISLPED, 2017)

An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop. - Nandish Mehta; Stephen G. Tell; Walker J. Turner; Lamar Tatro; Jih Ren Goh; C. Thomas Gray (IEEE J. Solid State Circuits, 2022)