Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ESA, 2005)

A low-power crossroad switch architecture and its core placement for network-on-chip. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ISLPED, 2005)

Fast Run-Time Power Monitoring Methodology for Embedded Systems. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ESA, 2006)

Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (DAC, 2006)

On a design of crossroad switches for low-power on-chip communication architectures. - Jih-Sheng Shen; Kuei-Chung Chang; Tien-Fu Chen (ISCAS, 2006)

A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability. - Jih-Sheng Shen; Pao-Ann Hsiung; Kuei-Chung Chang (ACSAC, 2008)

Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. - Kuei-Chung Chang; Jih-Sheng Shen; Tien-Fu Chen (ACM Trans. Design Autom. Electr. Syst., 2008)

Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication. - Jih-Sheng Shen; Pao-Ann Hsiung (IGI Global, 2010)

Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. - Jih-Sheng Shen; Chun-Hsian Huang; Pao-Ann Hsiung (DATE, 2010)

A Self-Adaptive Hardware/Software System Architecture for Ubiquitous Computing Applications. - Chun-Hsian Huang; Jih-Sheng Shen; Pao-Ann Hsiung (UIC, 2010)

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems. - Chun-Hsian Huang; Pao-Ann Hsiung; Jih-Sheng Shen (J. Syst. Archit., 2010)

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption. - Chun-Hsian Huang; Pao-Ann Hsiung; Jih-Sheng Shen (J. Syst. Archit., 2010)

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems. - Pao-Ann Hsiung; Chun-Hsian Huang; Jih-Sheng Shen; Cheng-Chi Chiang (ACM Trans. Reconfigurable Technol. Syst., 2010)

Network-on-Chip router design with Buffer-Stealing. - Wan-Ting Su; Jih-Sheng Shen; Pao-Ann Hsiung (ASP-DAC, 2011)

Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design. - Hung-Lin Chao; Chun-Yang Peng; Cheng-Chien Wu; Ken-Shin Huang; Chun-Hsien Lu; Jih-Sheng Shen; Pao-Ann Hsiung (FPT, 2013)

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption. - Jih-Sheng Shen; Pao-Ann Hsiung; Chun-Hsian Huang (Comput. Electr. Eng., 2013)

Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture. - Jih-Sheng Shen; Pao-Ann Hsiung; Juin-Ming Lu (HPCS, 2014)

Dynamic partially reconfigurable architecture for fast Fourier transform computation. - Hung-Lin Chao; Cheng-Chien Wu; Chun-Yang Peng; Chun-Hsien Lu; Jih-Sheng Shen; Pao-Ann Hsiung (Int. J. Embed. Syst., 2014)

Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip. - Jih-Sheng Shen; Pao-Ann Hsiung (IEEE Trans. Very Large Scale Integr. Syst., 2014)