Asymmetrical Write-assist for single-ended SRAM operation. - Jihi-Yu Lin; Ming-Hsien Tu; Ming-Chien Tsai; Shyh-Jye Jou; Ching-Te Chuang (SoCC, 2009)

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. - Ming-Hsien Tu; Jihi-Yu Lin; Ming-Chien Tsai; Shyh-Jye Jou; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

8T single-ended sub-threshold SRAM with cross-point data-aware write operation. - Yi-Wei Chiu; Jihi-Yu Lin; Ming-Hsien Tu; Shyh-Jye Jou; Ching-Te Chuang (ISLPED, 2011)

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. - Ming-Hsien Tu; Jihi-Yu Lin; Ming-Chien Tsai; Chien-Yu Lu; Yuh-Jiun Lin; Meng-Hsueh Wang; Huan-Shun Huang; Kuen-Di Lee; Wei-Chiang Shih; Shyh-Jye Jou; Ching-Te Chuang (IEEE J. Solid State Circuits, 2012)