A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. - Youngjoo Lee; Hoyoung Yoo; Jaehwan Jung; Jihyuck Jo; In-Cheol Park (IEEE J. Solid State Circuits, 2013)

Area-Efficient Multimode Encoding Architecture for Long BCH Codes. - Hoyoung Yoo; Jaehwan Jung; Jihyuck Jo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. - Byeong Yong Kong; Jihyuck Jo; Hyewon Jeong; Mina Hwang; Soyoung Cha; Bongjin Kim; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. - Jihyuck Jo; Hoyoung Yoo; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Low-Latency Low-Cost Architecture for Square and Cube Roots. - Jihyuck Jo; In-Cheol Park (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. - Jihyuck Jo; Soyoung Cha; Dayoung Rho; In-Cheol Park (IEEE J. Solid State Circuits, 2018)

Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. - Jihyuck Jo; Suchang Kim; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. - Suchang Kim; Jihyuck Jo; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads. - Seah Kim; Hyoukjun Kwon; Jinook Song; Jihyuck Jo; Yu-Hsin Chen; Liangzhen Lai; Vikas Chandra (CoRR, 2022)

DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads. - Seah Kim; Hyoukjun Kwon; Jinook Song; Jihyuck Jo; Yu-Hsin Chen; Liangzhen Lai; Vikas Chandra (ASPLOS (4), 2023)