CMOS image sensor with analog gamma correction using nonlinear single-slope ADC. - Seogheon Ham; Yonghee Lee; Wunki Jung; Seunghyun Lim; Kwisung Yoo; Youngcheol Chae; Jihyun Cho; Dongmyung Lee; Gunhee Han (ISCAS, 2006)

A 5000S/s Single-Chip Smart Eye-Tracking Sensor. - Dongsoo Kim; Jihyun Cho; Seunghyun Lim; Dongmyung Lee; Gunhee Han (ISSCC, 2008)

A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor network. - Jaehyuk Choi 001; Seokjun Park; Jihyun Cho; Euisik Yoon (ISSCC, 2012)

A 3.4µW CMOS image sensor with embedded feature-extraction algorithm for motion-triggered object-of-interest imaging. - Jaehyuk Choi 001; Seokjun Park; Jihyun Cho; Euisik Yoon (ISSCC, 2013)

7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes. - Seokjun Park; Jihyun Cho; Kyuseok Lee; Euisik Yoon (ISSCC, 2014)

A 3-D Camera With Adaptable Background Light Suppression Using Pixel-Binning and Super-Resolution. - Jihyun Cho; Jaehyuk Choi 001; Seong-Jin Kim; Seokjun Park; Jungsoon Shin; James D. K. Kim; Euisik Yoon (IEEE J. Solid State Circuits, 2014)

A 3.4-µW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging. - Jaehyuk Choi 001; Seokjun Park; Jihyun Cho; Euisik Yoon (IEEE J. Solid State Circuits, 2014)

12.3 PWM buck converter with >80% PCE in 45μA-to-4mA loads using analog-digital hybrid control for impiantale biomedical systems. - Sung-Yun Park; Jihyun Cho; Kyuseok Lee; Euisik Yoon (ISSCC, 2015)

Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression. - Adam E. Mendrela; Jihyun Cho; Jeffrey A. Fredenburg; Cynthia A. Chestek; Michael P. Flynn; Euisik Yoon (VLSIC, 2015)

Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ analog front-end architecture with 4.84fJ/C-s·mm2 energy-area product. - Sung-Yun Park; Jihyun Cho; Kyounghwan Na; Euisik Yoon (VLSIC, 2015)

An Energy/Illumination-Adaptive CMOS Image Sensor With Reconfigurable Modes of Operations. - Jaehyuk Choi 001; Seokjun Park; Jihyun Cho; Euisik Yoon (IEEE J. Solid State Circuits, 2015)

A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems. - Sung-Yun Park; Jihyun Cho; Kyuseok Lee; Euisik Yoon (IEEE Trans. Biomed. Circuits Syst., 2015)

A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression. - Adam E. Mendrela; Jihyun Cho; Jeffrey A. Fredenburg; Vivek Nagaraj; Theoden I. Netoff; Michael P. Flynn; Euisik Yoon (IEEE J. Solid State Circuits, 2016)

Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals. - Sung-Yun Park; Jihyun Cho; Kyuseok Lee; Euisik Yoon (IEEE J. Solid State Circuits, 2018)

Modular 128-Channel Δ-ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems. - Sung-Yun Park; Jihyun Cho; Kyounghwan Na; Euisik Yoon (IEEE J. Solid State Circuits, 2018)