A computational approach for identifying pathogenicity islands in prokaryotic genomes. - Sung Ho Yoon; Cheol-Goo Hur; Ho-Young Kang; Yeoun Hee Kim; Tae Kwang Oh; Jihyun F. Kim (BMC Bioinform., 2005)

Ensemble learning of genetic networks from time-series expression data. - Dougu Nam; Sung Ho Yoon; Jihyun F. Kim (Bioinform., 2007)

Towards pathogenomics: a web-based resource for pathogenicity islands. - Sung Ho Yoon; Young-Kyu Park; Soohyun Lee; Doil Choi; Tae Kwang Oh; Cheol-Goo Hur; Jihyun F. Kim (Nucleic Acids Res., 2007)

CFGP: a web-based, comparative fungal genomics platform. - Jongsun Park 002; Bongsoo Park; Kyongyong Jung; Suwang Jang; Kwangyul Yu; Jaeyoung Choi; Sunghyung Kong; Jaejin Park; Seryun Kim; Hyojeong Kim; Soonok Kim; Jihyun F. Kim; et al. (Nucleic Acids Res., 2008)

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. - Jenlung Liu; Sehyung Jeon; Tae-Kwang Jang; Dohyung Kim; Jihyun F. Kim; Jaejin Park; Hojin Park (A-SSCC, 2011)

A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. - Jong-Phil Hong; Sung-Jin Kim; Jenlung Liu; Nan Xing; Tae-Kwang Jang; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2012)

A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. - Tae-Kwang Jang; Nan Xing; Frank Liu 003; Jungeun Shin; Hyungreal Ryu; Jihyun F. Kim; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2013)

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. - Wooseok Kim; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (ISSCC, 2013)

A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. - Kangyeop Choo; Sung-Jin Kim; Wooseok Kim; Jihyun F. Kim; Taeik Kim; Hojin Park (CICC, 2014)

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. - Sung-Jin Kim; Wooseok Kim; Minyoung Song; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2015)

14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. - Minyoung Song; Taeik Kim; Jihyun F. Kim; Wooseok Kim; Sung-Jin Kim; Hojin Park (ISSCC, 2015)

PAIDB v2.0: exploration and analysis of pathogenicity and resistance islands. - Sung Ho Yoon; Young-Kyu Park; Jihyun F. Kim (Nucleic Acids Res., 2015)

A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. - Kangyeop Choo; Hyunik Kim; Wooseok Kim; Jihyun F. Kim; Taeik Kim; Hyung Jong Ko (ISSCC, 2018)