A cell-based power estimation in CMOS combinational circuits. - Jiing-Yuan Lin; Tai-Chien Liu; Wen-Zen Shen (ICCAD, 1994)

Transistor reordering rules for power reduction in CMOS gates. - Wen-Zen Shen; Jiing-Yuan Lin; Fong-Wen Wang (ASP-DAC, 1995)

A power modeling and characterization method for the CMOS standard cell library. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ICCAD, 1996)

CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. - Wen-Zen Shen; Jiing-Yuan Lin; Jyh-Ming Lu (ASP-DAC, 1997)

A power modeling and characterization method for macrocells using structure information. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ICCAD, 1997)

A structure-oriented power modeling technique for macrocells. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A new method for constructing IP level power model based on power sensitivity. - Heng-Liang Huang; Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ASP-DAC, 2000)

Integration, Verification and Layout of a Complex Multimedia SOC. - Chien-Liang Chen; Jiing-Yuan Lin; Youn-Long Lin (DATE, 2005)

DFM/DFY practices during physical designs for timing, signal integrity, and power. - Shi-Hao Chen; Ke-Cheng Chu; Jiing-Yuan Lin; Cheng-Hong Tsai (ASP-DAC, 2007)

Experiences of low power design implementation and verification. - Shi-Hao Chen; Jiing-Yuan Lin (ASP-DAC, 2008)