An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin. - Harold Pilo; Archie Allen; Jim Covino; Patrick Hansen; Steve Lamphier; Chris Murphy; Terry Traver; Pui Yee (IEEE J. Solid State Circuits, 2000)

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. - Harold Pilo; Darren Anand; John Barth 001; Steve Burns 001; Phil Corson; Jim Covino; Steve Lamphier (IEEE J. Solid State Circuits, 2003)

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)