Register Locking in an Asynchronous Microprocessor. - N. C. Paver; Paul Day; Stephen B. Furber; Jim D. Garside; John V. Woods (ICCD, 1992)

A CMOS VLSI Implementation of an Asynchronous ALU. - Jim D. Garside (Asynchronous Design Methodologies, 1993)

A micropipelined ARM. - Stephen B. Furber; Paul Day; Jim D. Garside; N. C. Paver; John V. Woods (VLSI, 1993)

AMULET1: A Micropipelined ARM. - Stephen B. Furber; Paul Day; Jim D. Garside; N. C. Paver; John V. Woods (COMPCON, 1994)

The Design and Evaluation of an Asynchronous Microprocessor. - Stephen B. Furber; Paul Day; Jim D. Garside; N. C. Paver; Steve Temple; John V. Woods (ICCD, 1994)

The AMULET2e cache system. - Jim D. Garside; Steve Temple; Rahul Mehra (ASYNC, 1996)

AMULET2e: An Asynchronous Embedded Controller. - Stephen B. Furber; Jim D. Garside; Steve Temple; Jianwei Liu; Paul Day; N. C. Paver (ASYNC, 1997)

A Result Forwarding Mechanism for Asynchronous Pipelined Systems. - D. A. Gilbert; Jim D. Garside (ASYNC, 1997)

AMULET1: A Asynchronous ARM Microprocessor. - John V. Woods; Paul Day; Stephen B. Furber; Jim D. Garside; N. C. Paver; Steve Temple (IEEE Trans. Computers, 1997)

AMULET3: a high-performance self-timed ARM microprocessor. - Stephen B. Furber; Jim D. Garside; D. A. Gilbert (ICCD, 1998)

Asynchronous Embedded Control. - Stephen B. Furber; Jim D. Garside; Steve Temple; Paul Day; Nigel C. Paver (Integr. Comput. Aided Eng., 1998)

AMULET3 Revealed. - Jim D. Garside; Stephen B. Furber; S.-H. Chung (ASYNC, 1999)

Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. - Mike J. G. Lewis; Jim D. Garside; L. E. M. Brackenbury (ASYNC, 1999)

Memory Faults in Asynchronous Microprocessors. - David W. Lloyd; Jim D. Garside; D. A. Gilbert (ASYNC, 1999)

AMULET2e: an asynchronous embedded controller. - Stephen B. Furber; James Garside; Peter A. Riocreux; Steve Temple; Paul Day; Jianwei Liu; Nigel C. Paver (Proc. IEEE, 1999)

AMULET3i - An Asynchronous System-on-Chip. - Jim D. Garside; W. J. Bainbridge; Andrew Bardsley; David M. Clark; David A. Edwards; Stephen B. Furber; David W. Lloyd; Siamak Mohammadi; J. S. Pepper; Steve Temple; John V. Woods; Jianwei Liu; et al. (ASYNC, 2000)

AMULET3: A 100 MIPS Asynchronous Embedded Processor. - Stephen B. Furber; David A. Edwards; Jim D. Garside (ICCD, 2000)

AMULET3i Cache Architecture. - Daranee Hormdee; Jim D. Garside (ASYNC, 2001)

A Practical Comparison of Asynchronous Design Styles. - David W. Lloyd; Jim D. Garside (ASYNC, 2001)

Power Management in the Amulet Microprocessors. - Stephen B. Furber; Aristides Efthymiou; Jim D. Garside; David W. Lloyd; Mike J. G. Lewis; Steve Temple (IEEE Des. Test Comput., 2001)

SPA - A Synthesisable Amulet Core for Smartcard pplications. - W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Peter A. Riocreux; Luis A. Plana (ASYNC, 2002)

An Asynchronous Victim Cache. - Daranee Hormdee; Jim D. Garside; Stephen B. Furber (DSD, 2002)

Adaptive Pipeline Depth Control for Processor Power-Management. - Aristides Efthymiou; Jim D. Garside (ICCD, 2002)

An adaptive serial-parallel CAM architecture for low-power cache blocks. - Aristides Efthymiou; Jim D. Garside (ISLPED, 2002)

Logic Design of Asynchronous Circuits (Tutorial Abstract). - Jordi Cortadella; Alexandre Yakovlev; Jim D. Garside (ASP-DAC/VLSI Design, 2002)

Adaptive Pipeline Structures fo Speculation Control. - Aristides Efthymiou; Jim D. Garside (ASYNC, 2003)

An asynchronous copy-back cache architecture. - Daranee Hormdee; Jim D. Garside; Stephen B. Furber (Microprocess. Microsystems, 2003)

SPA - a secure Amulet core for smartcard applications. - Luis A. Plana; Peter A. Riocreux; W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Z. C. Yu (Microprocess. Microsystems, 2003)

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. - Aristides Efthymiou; W. Suntiamorntut; Jim D. Garside; L. E. M. Brackenbury (ASYNC, 2004)

A CAM with mixed serial-parallel comparison for use in low energy caches. - Aristides Efthymiou; Jim D. Garside (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A Low-Power Processor Architecture Optimized forWireless Devices. - Aristides Efthymiou; Jim D. Garside; Ioannis Papaefstathiou (ASAP, 2005)

A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. - Charlie Brej; Jim D. Garside (VLSI Design, 2005)

Modernization of teaching in embedded systems design - an international collaborative project. - Saeid Nooshabadi; Jim D. Garside (IEEE Trans. Educ., 2006)

Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. - Andrew Robinson; Jim D. Garside (ACM Great Lakes Symposium on VLSI, 2007)

An adaptive bloom filter cache partitioning scheme for multicore architectures. - Konstantinos Nikas; Matthew Horsnell; Jim D. Garside (ICSAMOS, 2008)

Fault Tolerant Delay Insensitive Inter-chip Communication. - Yebin Shi; Steve B. Furber; Jim D. Garside; Luis A. Plana (ASYNC, 2009)

A Programmable Adaptive Router for a GALS Parallel System. - Jian Wu; Steve B. Furber; Jim D. Garside (ASYNC, 2009)

The Amulet chips: Architectural development for asynchronous microprocessors. - Jim D. Garside; Stephen B. Furber; Steve Temple; Viv Woods (ICECS, 2009)

SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. - Luis A. Plana; David M. Clark; Simon Davidson; Steve B. Furber; Jim D. Garside; Eustace Painkras; Jeffrey Pepper; Steve Temple; John Bainbridge (ACM J. Emerg. Technol. Comput. Syst., 2011)

Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration. - Geoffrey Ndu; Jim D. Garside (ARC, 2012)

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. - Jim D. Garside; Stephen B. Furber; Steve Temple; David M. Clark; Luis A. Plana (ASYNC, 2012)

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. - Eustace Painkras; Luis A. Plana; Jim D. Garside; Steve Temple; Simon Davidson; Jeffrey Pepper; David M. Clark; Cameron Patterson; Steve B. Furber (CICC, 2012)

Area efficient asynchronous SDM routers using 2-stage Clos switches. - Wei Song 002; Doug A. Edwards; Jim D. Garside; William J. Bainbridge (DATE, 2012)

Scalable communications for a million-core neural processing architecture. - Cameron Patterson; Jim D. Garside; Eustace Painkras; Steve Temple; Luis A. Plana; Javier Navaridas; Thomas Sharp; Steve B. Furber (J. Parallel Distributed Comput., 2012)

Automatic Controller Detection for Large Scale RTL Designs. - Wei Song 002; Jim D. Garside (DSD, 2013)

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (DSD, 2013)

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. - Eustace Painkras; Luis A. Plana; Jim D. Garside; Steve Temple; Francesco Galluppi; Cameron Patterson; David R. Lester; Andrew D. Brown; Steve B. Furber (IEEE J. Solid State Circuits, 2013)

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. - Javier Navaridas; Steve B. Furber; Jim D. Garside; Xin Jin 003; Mukaram M. Khan; David R. Lester; Mikel Luján; José Miguel-Alonso; Eustace Painkras; Cameron Patterson; Luis A. Plana; Alexander D. Rast; et al. (Parallel Comput., 2013)

Overview of the SpiNNaker System Architecture. - Steve B. Furber; David R. Lester; Luis A. Plana; Jim D. Garside; Eustace Painkras; Steve Temple; Andrew D. Brown (IEEE Trans. Computers, 2013)

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (ASYNC, 2014)

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. - Mahdi Jelodari Mamaghani; Jim D. Garside; William B. Toms; Doug A. Edwards (DSD, 2014)

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. - Wei Song 002; Guangda Zhang; Jim D. Garside (ACM Great Lakes Symposium on VLSI, 2014)

Automatic data path extraction in large-scale register-transfer level designs. - Wei Song 002; Jim D. Garside; Doug A. Edwards (ISCAS, 2014)

Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (Microprocess. Microsystems, 2014)

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. - Guangda Zhang; Jim D. Garside; Wei Song 002; Javier Navaridas; Zhiying Wang 003 (ASYNC, 2015)

De-elastisation: from asynchronous dataflows to synchronous circuits. - Mahdi Jelodari Mamaghani; Jim D. Garside; Doug A. Edwards (DATE, 2015)

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. - Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim D. Garside; Mikel Luján (FCCM, 2015)

Analysis of FPGA and software approaches to simulate unconventional computer architectures. - Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim D. Garside; Mikel Luján (ReConFig, 2015)

SpiNNaker - Programming Model. - Andrew D. Brown; Stephen B. Furber; Jeffrey S. Reeve; Jim D. Garside; Kier J. Dugan; Luis A. Plana; Steve Temple (IEEE Trans. Computers, 2015)

Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis. - Mahdi Jelodari Mamaghani; Danil Sokolov; Jim D. Garside (ACSD, 2016)

Automatic Clock: A Promising Approach toward GALSification. - Mahdi Jelodari Mamaghani; Milos Krstic; Jim D. Garside (ASYNC, 2016)

Parallel Hardware Merge Sorter. - Wei Song 002; Dirk Koch; Mikel Luján; Jim D. Garside (FCCM, 2016)

On-chip order-exploiting routing table minimization for a multicast supercomputer network. - Andrew Mundy; Jonathan Heathcote; Jim D. Garside (HPSR, 2016)

HAPPY: Hybrid Address-based Page Policy in DRAMs. - Mohsen Ghasempour; Aamer Jaleel; Jim D. Garside; Mikel Luján (MEMSYS, 2016)

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. - Mohsen Ghasempour; Aamer Jaleel; Jim D. Garside; Mikel Luján (MEMSYS, 2016)

Optimizing Indirect Branches in Dynamic Binary Translators. - Amanieu D'Antras; Cosmin Gorgovan; Jim D. Garside; Mikel Luján (ACM Trans. Archit. Code Optim., 2016)

Parallel distribution of an inner hair cell and auditory nerve model for real-time application. - Robert James; Jim D. Garside; Michael Hopkins; Luis A. Plana; Steve Temple; Simon Davidson; Steve B. Furber (BioCAS, 2017)

Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. - Gengting Liu; Jim D. Garside; Steve B. Furber; Luis A. Plana; Dirk Koch (FPL, 2017)

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Prateek Joshi; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; et al. (ISCAS, 2017)

Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; Matthias Eberlein; et al. (ISCAS, 2017)

Low overhead dynamic binary translation on ARM. - Amanieu D'Antras; Cosmin Gorgovan; Jim D. Garside; Mikel Luján (PLDI, 2017)

HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation. - Amanieu D'Antras; Cosmin Gorgovan; Jim D. Garside; John Goodacre; Mikel Luján (VEE, 2017)

Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. - Guangda Zhang; Wei Song 002; Jim D. Garside; Javier Navaridas; Zhiying Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. - Mantas Mikaitis; David R. Lester; Delong Shang; Steve B. Furber; Gengting Liu; Jim D. Garside; Stefan Scholze; Sebastian Höppner; Andreas Dixius (ARITH, 2018)

Resource Elastic Virtualization for FPGAs Using OpenCL. - Anuj Vaishnav; Khoa Dang Pham; Dirk Koch; James Garside (FPL, 2018)

Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application. - Robert James; Jim D. Garside; Luis A. Plana; Andrew Rowley; Steve B. Furber (IEEE Trans. Biomed. Circuits Syst., 2018)

Dynamic Power Management for Neuromorphic Many-Core Systems. - Sebastian Höppner; Bernhard Vogginger; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Georg Ellguth; Love Cederstroem; Luis A. Plana; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. - Luis A. Plana; Jim D. Garside; Jonathan Heathcote; Jeffrey Pepper; Steve Temple; Simon Davidson; Mikel Luján; Steve B. Furber (IEEE Access, 2020)

Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks. - Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim D. Garside; Mikel Luján (Simul. Model. Pract. Theory, 2020)

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. - Sebastian Höppner; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Marco Stolba; Florian Kelber; Bernhard Vogginger; Felix Neumärker; Georg Ellguth; Stephan Hartmann 002; Stefan Schiefer; et al. (CoRR, 2021)