Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. - Yin-Tsung Hwang; Jin-Fa Lin; Ming-Hwa Sheu; Chia-Jen Sheu (APCCAS, 2006)

A high speed and energy efficient full adder design using complementary & level restoring carry logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu; Cheng-Che Ho (ISCAS, 2006)

Low Power Multipliers Using Enhenced Row Bypassing Schemes. - Yin-Tsung Hwang; Jin-Fa Lin; Ming-Hwa Sheu; Chia-Jen Sheu (SiPS, 2007)

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu; Cheng-Che Ho (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Low Complexity Dual-Mode Pulse Generator Designs. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Low Power Pulse Generator Design Using Hybrid Logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Low power 10-transistor full adder design based on degenerate pass transistor logic. - Jin-Fa Lin; Yin-Tsung Hwang; Ming-Hwa Sheu (ISCAS, 2012)

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. - Yin-Tsung Hwang; Jin-Fa Lin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. - Yin-Tsung Hwang; Jin-Fa Lin; Ming-Hwa Sheu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through. - Jin-Fa Lin (IEEE Trans. Very Large Scale Integr. Syst., 2014)

MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging. - Shin-Shiang Wang; Yi-Chi Tien; Yin-Tsung Hwang; Jin-Fa Lin; Guo-Zua Wu (APCCAS, 2016)

Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors. - Jin-Fa Lin; Ming-Yan Tsai; Kun-Sheng Li; Yun-Rong Jiang; Yu-Shiang Cheng (J. Low Power Electron., 2016)

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. - Jin-Fa Lin; Ming-Hwa Sheu; Yin-Tsung Hwang; Chen-Syuan Wong; Ming-Yan Tsai (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. - Ming-Yan Tsai; Po-Yu Kuo; Jin-Fa Lin; Ming-Hwa Sheu (ISCAS, 2018)

Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation. - Wei-Hsuan Ma; Kuan-Ying Chang; Kuan-Ting Chen; Yin-Tsung Hwang; Jin-Fa Lin (ISOCC, 2019)

Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design. - Po-Yu Kuo; Chia-Hsin Hsieh; Jin-Fa Lin; Ming-Hwa Sheu; Yi-Ting Hung (IEICE Trans. Electron., 2019)

Semantic Lung Segmentation Using Convolutional Neural Networks. - Ching-Sheng Chang; Jin-Fa Lin; Ming-Ching Lee; Christoph Palm (Bildverarbeitung für die Medizin, 2020)

A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications. - Zhi-Zhong Wang; Yi-Hsuan Hung; Jun-Ting Wu; Zheng-Jie Hong; Jin-Fa Lin (ICCE-TW, 2021)

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications. - Ming-Hwa Sheu; Chang-Ming Tsai; Ming-Yan Tsai; Shih-Chang Hsia; S. M. Salahuddin Morsalin; Jin-Fa Lin (Sensors, 2021)

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design. - Jin-Fa Lin; Zheng-Jie Hong; Jun-Ting Wu; Xin-You Tung; Cheng-Hsueh Yang; Yu-Cheng Yen (Sensors, 2022)

Safety Monitoring System of Stamping Presses Based on YOLOv8n Model. - Tsoi-Na Fung; Yao-Hsuan Ku; Yu-Wei Chou; He-Shiang Yu; Jin-Fa Lin (IEEE Access, 2025)