Jin-Fu Li

According to our database1, Jin-Fu Li authored at least 110 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method.
Proceedings of the IEEE International Test Conference in Asia, 2020

2019
Testing of In-Memory-Computing 8T SRAMs.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Testing stuck-open faults of priority address encoder in content addressable memories.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

3D Test Wrapper Chain Optimization with I/O Cells Binding Considered.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
Conference Reports: Report on 2017 IEEE Asian Test Symposium.
IEEE Des. Test, 2018

Diagnosis of Resistive Nonvolatile-8T SRAMs.
Proceedings of the International SoC Design Conference, 2018

Modeling and testing comparison faults of memristive ternary content addressable memories.
Proceedings of the 23rd IEEE European Test Symposium, 2018

A channel-sharable built-in self-test scheme for multi-channel DRAMs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs.
Proceedings of the International Test Conference in Asia, 2017

A built-in self-test scheme for classifying refresh periods of DRAMs.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Fault modeling and testing of resistive nonvolatile-8T SRAMs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.
Proceedings of the 2016 IEEE International Test Conference, 2016

A built-in method for measuring the delay of TSVs in 3D ICs.
Proceedings of the 21th IEEE European Test Symposium, 2016

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Hierarchical Test Integration Methodology for 3-D ICs.
IEEE Des. Test, 2015

Fault modeling and testing of 1T1R memristor memories.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A hybrid built-in self-test scheme for DRAMs.
Proceedings of the VLSI Design, Automation and Test, 2015

Testing Inter-Word Coupling Faults of Wide I/O DRAMs.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs.
ACM Trans. Embed. Comput. Syst., 2014

A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Testing Disturbance Faults in Various NAND Flash Memories.
J. Electron. Test., 2014

The overview of 2014 CAD contest at ICCAD.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Testing of Non-volatile Logic-Based System Chips.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function.
J. Inf. Sci. Eng., 2013

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Special session 4C: Hot topic 3D-IC design and test.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An FPGA-based test platform for analyzing data retention time distribution of DRAMs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Built-In Self-Repair Scheme for the TSVs in 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells.
IEEE Trans. Computers, 2012

Test cost optimization technique for the pre-bond test of 3D ICs.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Area and reliability efficient ECC scheme for 3D RAMs.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A built-in self-test scheme for 3D RAMs.
Proceedings of the 2012 IEEE International Test Conference, 2012

Disturbance fault testing on various NAND flash memories.
Proceedings of the 17th IEEE European Test Symposium, 2012

On test and repair of 3D random access memory.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories.
J. Inf. Sci. Eng., 2011

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells.
IEEE Trans. Very Large Scale Integr. Syst., 2010

DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Built-in Method to Repair SoC RAMs in Parallel.
IEEE Des. Test Comput., 2010

Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A low-cost built-in self-test scheme for an array of memories.
Proceedings of the 15th European Test Symposium, 2010

A low-cost and scalable test architecture for multi-core chips.
Proceedings of the 15th European Test Symposium, 2010

Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A Test Integration Methodology for 3D Integrated Circuits.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Is 3D integration an opportunity or just a hype?
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks.
IEEE Micro, 2009

Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Efficient diagnosis algorithms for drowsy SRAMs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Testability Exploration of 3-D RAMs and CAMs.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs.
IEICE Trans. Inf. Syst., 2008

A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.
J. Electron. Test., 2008

A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Transparent-Test Methodologies for Random Access Memories Without/With ECC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults.
IET Comput. Digit. Tech., 2007

An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Raisin: Redundancy Analysis Algorithm Simulation.
IEEE Des. Test Comput., 2007

A Built-In Self-Repair Scheme for Multiport RAMs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Design of cost-efficient memory-based FFT processors using single-port memories.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Diagnosing scan chains using SAT-based diagnostic pattern generation.
Proceedings of the 2007 IEEE International SOC Conference, 2007

2006
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.
Proceedings of the 2006 IEEE International Test Conference, 2006

Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories.
Proceedings of the 11th European Test Symposium, 2006

A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
A built-in self-repair design for RAMs with 2-D redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Modeling and Testing Comparison Faults for Ternary Content Addressable Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

An error detection and correction scheme for RAMs with partial-write function.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Testing priority address encoder faults of content addressable memories.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories.
Proceedings of the 2005 Design, 2005

Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults.
IEICE Trans. Inf. Syst., 2004

Efficient Test Methodologies for Conditional Sum Adders.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An Efficient Diagnosis Scheme for Random Access Memories.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Built-in redundancy analysis for memory yield improvement.
IEEE Trans. Reliab., 2003

Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.
J. Electron. Test., 2003

A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Efficient FFT network testing and diagnosis schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2002

A Hierarchical Test Methodology for Systems on Chip.
IEEE Micro, 2002

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.
J. Electron. Test., 2002

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.
J. Electron. Test., 2002

Testing and Diagnosing Embedded Content Addressable Memories.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

A Hierarchical Test Scheme for System-On-Chip Designs.
Proceedings of the 2002 Design, 2002

2001
March-based RAM diagnosis algorithms for stuck-at and coupling faults.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Memory fault diagnosis by syndrome compression.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
A built-in self-test and self-diagnosis scheme for embedded SRAM.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Testable and Fault Tolerant Design for FFT Networks.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999


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