A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. - Jin-Fu Lin; Soon-Jyh Chang (ISCAS, 2006)

A Reduced Code Linearity Test Method for Pipelined A/D Converters. - Jin-Fu Lin; Te-Chieh Kung; Soon-Jyh Chang (ATS, 2008)

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique. - Jin-Fu Lin; Soon-Jyh Chang; Chih-Hao Huang (Asian Test Symposium, 2009)

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique. - Jin-Fu Lin; Soon-Jyh Chang; Chun-Cheng Liu; Chih-Hao Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs. - Jin-Fu Lin; Hsin-Wen Ting (J. Electron. Test., 2011)

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages. - Jin-Fu Lin; Soon-Jyh Chang (IEICE Trans. Electron., 2011)

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. - Jin-Fu Lin; Soon-Jyh Chang; Te-Chieh Kung; Hsin-Wen Ting; Chih-Hao Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 1-V CDS bandgap reference without on-chip resistors. - Peng-Yu Chen; Soon-Jyh Chang; Chung-Ming Huang; Jin-Fu Lin (APCCAS, 2012)

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology. - Sheng-Hsiung Lin; Jin-Fu Lin; Guan-Ying Huang; Soon-Jyh Chang (APCCAS, 2012)

Topology algorithm based on link maintenance time for mobile ad hoc using directional antennas. - Jin-Fu Lin; Peng Bai; Jian-Xun Wang 001; Ying Wang; Tao Wang (Int. J. Wirel. Mob. Comput., 2015)

Cross-Domain Hallucination Network for Fine-Grained Object Recognition. - Jin-Fu Lin; Yen-Liang Lin; Erh-Kan King; Hung-Ting Su; Winston H. Hsu (CVPR Workshops, 2018)