VLSI Layout Compaction with Grid and Mixed Constraints. - Jin-Fuw Lee; Donald T. Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

A new framework of design rules for compaction of VLSI layouts. - Jin-Fuw Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

A Layout Compaction Algorithm with Multiple Grid Constraints. - Jin-Fuw Lee (ICCD, 1991)

HIMALAYAS - a hierarchical compaction system with a minimized constraint set. - Jin-Fuw Lee; Donald T. Tang (ICCAD, 1992)

A performance-aimed cell compactor with automatic jogs. - Jin-Fuw Lee; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

An Algorithm for Incremental Timing Analysis. - Jin-Fuw Lee; Donald T. Tang (DAC, 1995)

A timing analysis algorithm for circuits with level-sensitive latches. - Jin-Fuw Lee; Donald T. Tang; Chak-Kuen Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Methods for calculating coupling noise in early design: a comparative analysis. - Khalid Rahmat; José Neves 002; Jin-Fuw Lee (ICCD, 1998)

On the Signal Bounding Problem in Timing Analysis. - Jin-Fuw Lee; Daniel L. Ostapko; Jeffery Soreff; C. K. Wong (ICCAD, 2001)

Yield estimation of SRAM circuits using "Virtual SRAM Fab". - Aditya Bansal; Rama N. Singh; Rouwaida Kanj; Saibal Mukhopadhyay; Jin-Fuw Lee; Emrah Acar; Amith Singhee; Keunwoo Kim; Ching-Te Chuang; Sani R. Nassif; Fook-Luen Heng; Koushik K. Das (ICCAD, 2009)