Physical design implementation of segmented buses to reduce communication energy. - Jin Guo 001; Antonis Papanikolaou; Pol Marchal; Francky Catthoor (ASP-DAC, 2006)

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. - Jin Guo 001; Antonis Papanikolaou; Pol Marchal; Francky Catthoor (SLIP, 2006)

Topology exploration for energy efficient intra-tile communication. - Jin Guo 001; Antonis Papanikolaou; Francky Catthoor (ASP-DAC, 2007)

Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. - Jin Guo 001; Antonis Papanikolaou; H. Zhang; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A tool flow for predicting system level timing failures due to interconnect reliability degradation. - Jin Guo 001; Antonis Papanikolaou; Michele Stucchi; Kristof Croes; Zsolt Tokei; Francky Catthoor (ACM Great Lakes Symposium on VLSI, 2008)