Digitally tuneable on-chip resistor in CMOS for high-speed data transmission. - Kyoung-Hoi Koo; Jin-Ho Seo; Jae-Whui Kim (ISCAS (1), 2003)

A slew-rate controlled output driver using PLL as compensation circuit. - Soon-Kyun Shin; Seok-Min Jung; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (IEEE J. Solid State Circuits, 2003)

A new level shifter in ultra deep sub-micron for low to wide range voltage applications. - Kyoung-Hoi Koo; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (SoCC, 2004)

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron. - Kyoung-Hoi Koo; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (ISCAS (2), 2005)

A versatile I/O with robust impedance calibration for various memory interfaces. - Kyoung-Hoi Koo; Soo-Kyung Lee; Jin-Ho Seo; Myeong-Lyong Ko; Jae-Whui Kim (ISCAS, 2006)

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. - Jun-Hyun Bae; Jin-Ho Seo; Hwan-Seok Yeo; Jae-Whui Kim; Jae-Yoon Sim; Hong-June Park (CICC, 2007)

A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor. - Jae-Hong Kim; Wun-ki Jung; Seung-hyun Lim; Yu-jin Park; Won-Ho Choi; Yun-Jung Kim; Chang-eun Kang; Jihun Shin; Kyojin Choo; Won-baek Lee; Jin-kyeong Heo; Byung-jo Kim; et al. (ISSCC, 2012)