A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. - Sung-Ho Wang; Jeongpyo Kim; Joonsuk Lee; Hyoung Sik Nam; Young Gon Kim; Jae Hoon Shim; Hyung Ki Ahn; Seok Kang; Bong Hwa Jeong; Jin-Hong Ahn; Beomsup Kim (IEEE J. Solid State Circuits, 2001)

CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. - Kyeong-Sik Min; Young-Hee Kim; Jin-Hong Ahn; Jin-Yong Chung; Takayasu Sakurai (ISCAS (5), 2002)

A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. - Se Jun Kim; Sang Hoon Hong; Jae-Kyung Wee; Joo-Hwan Cho; Pil Soo Lee; Jin-Hong Ahn; Jin-Yong Chung (IEEE J. Solid State Circuits, 2002)

A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. - Kyeong-Sik Min; Young-Hee Kim; Daejeong Kim; Dong Myeong Kim; Jin-Hong Ahn (ASP-DAC, 2004)

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. - Dong-Uk Lee; Hyun-Woo Lee; Ki Chang Kwean; Young-Kyoung Choi; Hyong Uk Moon; Seung-Wook Kwack; Shin-Deok Kang; Kwan-Weon Kim; Yong Ju Kim; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn; et al. (ISSCC, 2006)

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. - Ki-Won Lee; Joo-Hwan Cho; Byoung-Jin Choi; Geun-Il Lee; Ho-Don Jung; Woo-Young Lee; Ki-Chon Park; Yongsuk Joo; Jaehoon Cha; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn (IEEE J. Solid State Circuits, 2007)

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Shin-Deok Kang; Ji-Yeon Yang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; Young-Ju Kim 001; Won-Jun Choi; Keun-Soo Song; Sang-Hoon Shin; et al. (ISSCC, 2008)

A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application. - Bong Hwa Jeong; Jongwon Lee; Yin Jae Lee; Tae Jin Kang; Joo Hyeon Lee; Duck Hwa Hong; Jae Hoon Kim; Eun Ryeong Lee; Min Chang Kim; Kyung Ha Lee; Sang Il Park; Jong Ho Son; et al. (ISSCC, 2009)

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. - Hyun-Woo Lee; Won-Joo Yun; Young-Kyoung Choi; Hyang-Hwa Choi; Jong-Jin Lee; Ki-Han Kim; Shin-Deok Kang; Ji-Yeon Yang; Jae-Suck Kang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; et al. (ISSCC, 2009)