Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

Validation of Cuffless Blood Pressure Monitoring Using Wearable Device. - Jin-Hyeok Baek; Junho Kim; Namho Kim; Daeho Lee; Sung-Min Park 001 (TENCON, 2018)

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. - Jin-Hyeok Baek; Chang-Kyo Lee; Kiho Kim; Daesik Moon; Gil-Hoon Cha; Jin-Seok Heo; Min-Su Ahn; Dong-Ju Kim; Jae-Joon Song; Seokhong Kwon; Jongmin Kim; Kyung-Soo Kim; et al. (VLSI Circuits, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. - Jin-Seok Heo; Kihan Kim; Dong-Hoon Lee; Chang-Kyo Lee; Daesik Moon; Kiho Kim; Jin-Hyeok Baek; Sung-Woo Yoon; Hui-Kap Yang; Kyungryun Kim; Youngjae Kim; Bokgue Park; et al. (VLSI Circuits, 2019)

A Flexible Patch-Type Strain Sensor Based on Polyaniline for Continuous Monitoring of Pulse Waves. - Sehong Kang; Vega Pradana Rachim; Jin-Hyeok Baek; Seung Yong Lee; Sung-Min Park 001 (IEEE Access, 2020)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

High Sampling Rate Smartphone-PPG via Built-in Rolling Shutter Image Sensor. - Vega Pradana Rachim; Jin-Hyeok Baek; Youngsoo Kim; Younho Kim; Sung-Min Park 001 (IEEE Internet Things J., 2023)

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Dong-Hun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (IEEE J. Solid State Circuits, 2024)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)